Summary
Overview
Work History
Education
Skills
Accomplishments
Certification
Timeline
Generic
JAGMEET SINGH

JAGMEET SINGH

Summary

IPV4 NETWORKING & SECURITY VLANS AND VLAN TRUNKING PERFORMANCE OPTIMIZATION SCALABILITY & RELIABILITY HARDWARE-SOFTWARE CO-DESIGN VALIDATION MODELS HANSPAL MASTER ARCHITECT ABOUT ME I bring a proven track record of delivering innovative solutions across diverse industries, with a rich background in firmware development, system architecture, and project management. I have spearheaded the development of cutting-edge embedded/networking systems and established teams in complex software design projects with expertise that spans the entire product lifecycle. With over two decades of experience in Networking / Embedded systems and Agile Software Development, I possess a strong foundation in technical leadership. Equipped with expertise in a variety of programming languages and networking protocols and tools, I am prepared to thrive in roles spanning Systems Engineer to Technology Solutions Architect as well as Product Management.

Overview

2013
2013
years of professional experience
1
1
Certification

Work History

ESSCI - ELECTRONICS SKILL SECTOR

EMTECH FOUNDATION
  • SME (Embedded Systems Software) for National Qualification Pack / Standard for the Skill India Initiative
  • Involved in an advisory role as a founding member for this Embedded Electronics training centre

SYSTEMS SOFTWARE ARCHITECT

HEWLETT PACKARD ENTERPRISE
05.2018
  • Pioneered AVB architecture development for HPE switches, innovating industry standards
  • Established and led a team from inception, achieving PTP delivery across diverse HPE-Aruba platforms
  • Assumed the Architect role for VSX team, ensuring timely releases through effective leadership
  • Explored Private VLAN viability on Broadcom-based switching platforms, enhancing design strategies
  • Key achievements
  • Filed patent in 2023: "Method for implementing PTP Boundary-Clock with VSX," showcasing innovation
  • Achieved successful delivery in 2022: PTP Transparent Clock with VSX and VSF, meeting objectives
  • Recognized at 2019 HPE Hackathon for developing route optimization model for time-series traffic prediction.

SENIOR TECHNICAL LEAD

ERICSSON INDIA PVT LTD
01.2018
  • Developed Traffic-Steering for IPSEC to cater to specific customer scenarios, including NAT and roaming
  • Led development efforts to enable subscriber support across bridge-virtual-instances (BVI)
  • Designed and implemented an L2TP LNS for Spider-Based 20x10GE cards, encompassing both design and development phases
  • Assumed Agile OPO responsibilities to define and manage backlogs for L2TP LNS and BVI features
  • Solely devised Sync-control and RPC features, enhancing system stability and performance
  • Spearheaded Technology-Leadership Project on an SDN-based Load-balancer utilizing Open Virtual
  • Switch
  • Integrated PPP/CHDLC protocols into the spider-based POS card with OCn interfaces for SSR routers
  • Traveled to Budapest, Hungary, for POS packet-forwarding software deployment during board bring-up
  • Acted as the Point of Contact (PoC) for the Converged Packet Gateway (3GPP CPG) product, resolving numerous escalations
  • Key achievements
  • Awarded EngiNerd in 2017 for "Smart Conference Rooms with IoT," showcasing innovation
  • Successfully completed Ericsson L1 assessment in 2016, demonstrating management and leadership skills
  • Earned Ericsson ACE and Rock-star Awards in 2015-16 for Quality Focus and delivering key projects
  • Recognized with Ericsson PDUIP Routers Gold Partnership Award in 2014 for Quality Focus and Drive
  • Received "Best Ericsson Innova 2013" award at the Global Ericsson ceremony in San Jose, California
  • Achieved the Ericsson Innova Best Experimentation award in 2012 for a QT based Application software.

SENIOR MEMBER TECHNICAL STAFF

TRANSWITCH SEMICONDUCTORS INDIA PVT LTD
01.2009
  • Contributed architectural insights on IEEE-1588 for the T-series routers, enhancing functionality
  • Strategized diagnostics planning for T-series 4xOC-48 modules, optimizing performance
  • Conducted performance tests on 4xOC-48 modules with Frame-relay, Cisco HDLC, and PPP protocols
  • Implemented translation-tables in the EZchip Network-processor and device-driver for seamless operation
  • Conducted Class-Of-Service Unit-tests using Spirent Router Tester, ensuring reliability
  • Key achievements
  • In 2012, filed Juniper Invention Disclosure for "Achieving time synchronization amongst line-cards."
  • Runner-up in the 2010 Juniper Technical Paper contest for "Clock Synchronization using IEEE-1588.", Led the design and development of Ethernet Packet-Processing Fast-Path Firmware, encompassing various components such as Classifier, Forwarder, Filter, QoS, trTCM, srTCM, and WRED algorithms for
  • TranSwitch's multi-core parallel-processing system
  • Collaborated with Systems' team in the US development center and Tool-chain team in the Switzerland development center
  • Developed clock-synchronization algorithms based on stochastic processes/models
  • Utilized Frequency Counter, Time Monitor, CRO, and Logic Analyzers to verify results under different network conditions emulated through IXIA in the lab environment
  • Engaged in training on Project Management (PMBoK), Statistics, and Microsoft Project
  • Established coding conventions for Customizable Multi-core Platform
  • Created a generic Linux device-driver compatible with major TranSwitch products
  • Successfully ported Monta Vista Linux Kernel 3.1 to TranSwitch Power-PC based evaluation boards
  • Designed MEF compatible device-driver code-generator for standard user experience across devices
  • Implemented VLAN module in the device-driver
  • Developed a Demo-Application on VxWorks to demonstrate SONET protection switching
  • Key achievements

SENIOR SOFTWARE ENGINEER

JUNIPER NETWORKS
10.2009 - 04.2012
  • Led the entire process from feasibility to design and development of Synchronous Ethernet on Terabit routers.

SOFTWARE ENGINEER

FREESCALE SEMICONDUCTORS, Adapted
06.2004 - 01.2005
  • MetroTRK (an Embedded Debug Agent) to function as a boot loader
  • Rectified Embeddable Flashing algorithms for improved performance
  • Collaborated with the Metrowerks CodeWarrior Debugger Development team
  • Transferred MetroTRK onto various Boards with diverse BSPs
  • Employed TCL scripting to automate XML Register detailing in CodeWarrior 2.1 for ARM.

EMBEDDED SYSTEMS ENGINEER

ALBA CONTROL SYSTEMS LTD
05.2003 - 06.2004
  • Collaborated on the development of ARM and Linux-based Access Control System with IIT-Delhi
  • Enhanced the Device-Driver and contributed to Front-end development through re-engineering efforts
  • Developed various products, including Barrier Control and Automated Car Parking systems, using C and
  • Assembly Language
  • Contributed to a six-member team developing a cost-effective Intel MCS-51 Access Control System
  • Successfully integrated and deployed projects for a range of clients such as Oracle, HCL, Ericsson
  • Fibcom, Hutch, GE, and Indian Airlines.

Education

POST GRADUATE - IT Management

All India Management
2009

BACHELOR OF - Electronics & Communications

CR State College of Engineering
2002

Phy - Chem Math + Bio

SENIOR SECONDARY
1998

Apeejay School
1996

Skills

  • SECONDARY SCHOOL
  • General CBSE
  • Apeejay School
  • EXPERTISE
  • SYSTEM ARCH AND
  • DESIGN
  • ARCHITECTURE MODELING
  • DESIGN AND INTEGRATION
  • HLD AND LLD DESIGN PATTERNS
  • BAREMETAL AND RTOS
  • LOW-LEVEL (C/ASSEMBLY)
  • DEVICE DRIVER DEVELOPMENT
  • FIRMWARE DEVELOPMENT
  • EMBEDDED LINUX DEVELOPMENT
  • HARDWARE ABSTRACTION LAYERS
  • WEB APPLICATIONS
  • LAMP STACK
  • JAVACRIPT, CSS AND HTML
  • SVELTE FRAMEWORK
  • WORDPRESS CMS
  • RESTFUL APIS
  • WEB HOSTING (AWS / UNMANAGED)
  • CONTAINERIZATION (DOCKER)
  • LOAD BALANCING
  • SQL AND JSON BASED DBS
  • LANGUAGES
  • ENGLISH
  • HINDI
  • PUNJABI
  • HOBBIES
  • SWIMMING
  • BASKETBALL
  • INSTRUMENTAL MUSIC
  • TRAVELING
  • PERSONAL
  • ATTRIBUTES
  • ANALYTICAL & STRATEGIC
  • AMBITIOUS & INNOVATIVE
  • HIGH LEVEL OF INTEGRITY

Accomplishments

  • Granted Patent in 2010: "Packet Processing System On chip device" International Pub
  • No.:
  • WO/2010/076649
  • Granted Patent in 2008: "Method and Apparatus for determining Dynamic Queue Fill Levels" #MUM/2008.

Certification

PLANNING AND EXECUTION TEAM COLLABORATION AGILE SOFTWARE DEVELOPMENT RISK MANAGEMENT AND MITIGATION CROSS-FUNCTIONAL COORDINATION STAKEHOLDER COMMUNICATION RESOURCE ALLOCATION SYSTEM S/W DEVELOPMENT C/C++ PROGRAMMING SCRIPTING (PYTHON, TCL) COMPLETE SDLC VERSION CONTROL - GIT CROSS-PLATFORM DEVELOPMENT N/W TECHNOLOGIES IEEE 1588 (PTP) AUDIO VIDEO BRIDGING (AVB) SYNCHRONOUS ETHERNET IPV4 NETWORKING & SECURITY VLANS AND VLAN TRUNKING QUALITY OF SERVICE (QOS) IPV4 NETWORKING DATAPLANE AND PACKET PROCESSING ETHERNET PROTOCOLS (IEEE 802.3) EMBEDDED SYSTEMS RASPI/ATMEL/ESP8266

Timeline

SYSTEMS SOFTWARE ARCHITECT

HEWLETT PACKARD ENTERPRISE
05.2018

SENIOR TECHNICAL LEAD

ERICSSON INDIA PVT LTD
01.2018

SENIOR SOFTWARE ENGINEER

JUNIPER NETWORKS
10.2009 - 04.2012

SENIOR MEMBER TECHNICAL STAFF

TRANSWITCH SEMICONDUCTORS INDIA PVT LTD
01.2009

SOFTWARE ENGINEER

FREESCALE SEMICONDUCTORS, Adapted
06.2004 - 01.2005

EMBEDDED SYSTEMS ENGINEER

ALBA CONTROL SYSTEMS LTD
05.2003 - 06.2004

BACHELOR OF - Electronics & Communications

CR State College of Engineering

Phy - Chem Math + Bio

SENIOR SECONDARY

Apeejay School

ESSCI - ELECTRONICS SKILL SECTOR

EMTECH FOUNDATION

POST GRADUATE - IT Management

All India Management

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