Summary
Overview
Work History
Education
Skills
Certification
Timeline
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Yogesh Patil

Bengaluru

Summary

Lead Design Engineer with extensive experience in power estimation, modelling, and optimisation at Qualcomm. Demonstrated expertise in DDRSS power projection, debugging flow issues, and developing automation for power estimation. Achieved up to 20% power savings in low bandwidth scenarios for cache controllers. Previous roles include Digital Design Engineer at Intel Corporation, focusing on SRAM design, dynamic timing analysis, power convergence.

Overview

9
9
years of professional experience
1
1
Certification

Work History

Lead Design Engineer

Qualcomm
10.2022 - Current
  • Power estimation, modelling and optimization in DDRSS
  • Involves power projection for various subIPs that includes cache controller, memory contoller and NoCIP
  • Debugged mutliple flow issues, fsdb debug related to bandwith, transaction types
  • Developed multiple automations to improve power analysis and suggest required optimization
  • Proposed power saving features to RTL/arch team showing upto 20% savings in low BW scenarions for cache contoller
  • Explored DRAM power calculation and proposed possible DRAM voltage (VDD2H) scaling
  • Developed flow that intergrates TLM and power models to provide early power impact analysis.

Digital Design Engineer

Intel Corporation
10.2020 - 10.2022
  • I am working on SRAM design in latest process technologies (INTEL 20A) with respect to performance, stability
  • Dynamic timing analysis - Race condition definition, simulation and fixes
  • Vmin simulations - Read/Write performance and stability, VF curve analysis
  • Innovation - Analysis of write-assist, read-assist techniques, floating bitline, negative bitline, partial precharge
  • Power - Leakage analysis for PDK comparison

Senior Design Engineer

Mirafra Technologies
10.2019 - 10.2020
  • Synthesis - UPF based, Physical aware synthesis (DC) for integrated wireless and bluetooth chip in TSMC 28nm (low-power) and then transition to 22nm node
  • Constraints integration of IPs at SoC level
  • Tried multiple recipes with different DC variables, frequency and track libraries to get comparison picture of area, leakage power and timing QoR
  • Power intent verification (CLP)
  • Good understanding of IEEE-1801 UPF, Power Supply Network(PSN) and MSVs
  • Scripting : Manual insertion of low power cells (zero pin retention) that not supported in DC, clock properties, etc (bash, tcl scripts)

Design Engineer

Intel Corporation
07.2015 - 01.2018
  • Static Timing Analysis (STA) - Block level timing closures of various complexities
  • Core level timing analysis with wall function(core health metric) and optimization tool
  • Cost analysis (Timing, Power and layout perspectives) for scan, RTL features and technology node transition get the targeted performance improvement
  • Power optimization
  • Driving section(DL3) level power convergence right from TR stage
  • Coordinated with RTL and PDEs for cost-effort analysis of power and other features
  • Deployed necessary tool add-ons towards easy power convergence working with DAs

Education

Masters - Electronics System

Indian Institute of Technology, Bombay
07.2015

Skills

  • Power estimation
  • Power modelling
  • Power Optimization
  • SRAM Design
  • Static Timing Analysis
  • Low power design
  • High speed design
  • Scripting - bash, python, tcl
  • Advanced Synthesis with Genus Stylus

Certification

  • Common UI v19.1 Exam, 05/01/20
  • Conformal Equivalence Checking v19.1 Exam, 05/01/20
  • Tempus Signoff Timing Analysis and Closure v19.1 Exam, 05/01/20

Timeline

Lead Design Engineer

Qualcomm
10.2022 - Current

Digital Design Engineer

Intel Corporation
10.2020 - 10.2022

Senior Design Engineer

Mirafra Technologies
10.2019 - 10.2020

Design Engineer

Intel Corporation
07.2015 - 01.2018

Masters - Electronics System

Indian Institute of Technology, Bombay

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