TUSHANT VERMA
DL
Summary
Results-driven professional with a strong technical skillset and academic background, seeking a challenging and dynamic position within top companies across diverse industries. Demonstrated ability to adapt quickly to new skills and technologies, consistently delivering exceptional results within designated timeframes. Valuable internship experience at NXP Semiconductors Bengaluru Onsite, specializing in the AMS Verification domain.
Overview
3
3
years of professional experience
Work History
AMS VERIFICATION INTERN
NXP Semiconductor
07.2024 - Current
- Worked on Cadence Virtuoso tool to verify the functionality of different models and schematic.
- Modelled DUT and testbench in system verilog for top level verification.
- Developed WREAL, Electrical model and testbench for CDR, BGR, LDO, LCR and other analog blocks
- Generated .lib files using Cadence Liberate
- Verified the CDR calibration in live project
- Made Configuration files in live project
- Developed a good understanding of Spectre Simulator, LSF and GVIM environment.
Senior Analyst
Capgemini India
08.2022 - 08.2023
- Worked on Salesforce CRM Tool during my tenure
- Tested different JIRA stories on live project
Education
M.Tech - VLSI Design and Embedded Systems
Delhi Technological University(DTU)
New Delhi, India06-2025
Bachelor of Technology(B.Tech) - Electronics And Communication Engineering
INDIAN INSTITUTE OF INFORMATION TECHNOLOGY (IIIT)
Una, Himachal Pradesh06-2022
Intermediate - Science
DAYAWATI MODI ACADEMY
Meerut, India01-2017
Skills
- Static Timing Analysis
- Verilog
- Verilog AMS
- Low Power VLSI Design
- System Verilog
- UVM Basics
- Cadence Virtuoso
- Cadence Liberate
- Physical Design Flow
- ASIC Design Flow
- Good Debugging Skills
- SimVision
Accomplishments
- Qualified GATE 2023 in EC branch with 90 percentiles.
- NPTEL Certified in Digital Electronics
Projects
Transistor Stacking Technique in Combinational Circuits.
• Implemented transistor stacking technique in circuits like NAND gate and NOR gate to reduce the power dissipation.
• The logic gates were designed using 130nm technology parameter and are simulated using LTSpice.
Vending Machine using FSM.
• Implemented a Vending Machine FSM using Verilog in Xilinx Vivado ISE and verified using a testbench.
Timeline
AMS VERIFICATION INTERN
NXP Semiconductor
07.2024 - Current
Senior Analyst
Capgemini India
08.2022 - 08.2023
M.Tech - VLSI Design and Embedded Systems
Delhi Technological University(DTU)
Bachelor of Technology(B.Tech) - Electronics And Communication Engineering
INDIAN INSTITUTE OF INFORMATION TECHNOLOGY (IIIT)
Intermediate - Science
DAYAWATI MODI ACADEMY
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