Aashish Kunnummal
Bengaluru,KA
Summary
ASIC Physical Design Engineer who has taken a 40 nm microprocessor block from floorplan to sign-off-ready layout across multiple full-time internships using Synopsys ICC2 and PrimeTime. Deep hands-on strength in floorplanning, power planning, placement, CTS, routing, and MCMM timing analysis, with measurable impact—WNS improved from –0.35 ns to +0.05 ns, and IR-drop reduced to signoff limits. Known for disciplined execution, power integrity focus, and working comfortably inside production-style ASIC design environments where results matter more than theory.
Overview
1
1
year of professional experience
1
1
Certification
Work History
ASIC Physical Design of Microprocessor Block (RTL-to-GDSII | 40nm Technology Node)
RV-SKILLS Center For Emerging Technologies
04.2025 - 09.2025
- Executed complete ASIC flow: logic synthesis, floorplanning, power grid creation, placement optimization, CTS, routing, ECO, and signoff.
- Designed hierarchical floorplan with optimized macro placement to minimize latency and congestion.
- Achieved first-pass MCMM timing closure, improving WNS from -0.35 ns to +0.05 ns using buffer optimization, VT swapping, gate resizing, and ECO restructuring.
- Reduced clock skew by 18% using multi-source CTS and H-tree strategy, improving overall frequency margin.
- Implemented UPF-based low-power architecture with DVFS, multi-Vt, and power gating-achieving 18% leakage and 12% dynamic power reduction.
- Minimized IR drop from 7.2% to
- Improved routing congestion by 22% via macro reorientation, non-default routing rules (NDRs), and track reservation techniques.
- Resolved 100+ DRC and 20+ LVS violations to achieve full signoff-clean layout using Calibre (DRC/LVS/EM/DFM).
- Generated tape-out-ready GDSII fully compliant with IR/EM reliability and manufacturability guidelines.
- Developed TCL/Python-based automation scripts to streamline placement, STA report extraction, and ECO closure-reducing overall flow runtime by 30%.
Engineering Intern – LCA Tejas Division
Hindustan Aeronautics Limited (HAL) | Bengaluru
Bengaluru
11.2024 - 03.2025
- Worked with the LCA Tejas engineering division, gaining exposure to aerospace-grade electronic systems, design documentation, and validation workflows.
- Assisted in engineering documentation review, subsystem-level analysis, and technical data validation under senior engineering teams.
- Observed defense-grade quality, safety, and compliance standards followed in large-scale production environments.
- Gained an understanding of cross-functional engineering coordination, design reviews, and program execution lifecycle.
- Strengthened discipline in engineering documentation, process adherence, and technical communication.
Education
Advanced Diploma - ASIC Design
RV-SKILLS Center For Emerging Technologies
Bangalore, Karnataka09.2025
Bachelors of Engineering - Electronics and Communication Engineering
SJB Institute of Technology
Bengaluru06.2025
Higher Secondary - Science
Kendriya Vidyalaya Hebbal
Bengaluru03.2021
Skills
- Floorplanning
- Physical design
- Power Planning
- Standard Cell Placement & Optimization
- Clock Tree Synthesis
- Global & Detail Routing
- Timing- Driven & Congestion- Aware Design
- Design Closure
- TIMING & POWER ANALYSIS
- Static Timing Analysis
- IR Drop Mitigation
- Signal Integrity & Noise Analysis
- LOW- POWER METHODOLOGIES
- UPF
- Power gating
- Multi- Vt
- EDA TOOLS
- Synopsys ICC2
- PrimeTime
- TCL
- Python
- Automation of PD flows
Certification
- Advanced Diploma in ASIC Design, 04/2025, 09/2025, RV-SKILLS Center for Emerging Technologies
- ROBO AI Certification, 08/2024, My Equation
Projects
ASIC physical design of microprocessor block (40 nm technology node)
RV-SKILLS Center for Emerging Technologies, Apr 2025 – Sep 2025
Project description: Worked on an industry-scale microprocessor block, executing end-to-end ASIC physical design activities under tape-out oriented conditions.
Key responsibilities and achievements:
- Executed the complete ASIC implementation flow, including logic synthesis, floorplanning, power grid creation, placement optimization, clock tree synthesis (CTS), routing, and physical signoff
- Designed a hierarchical floorplan with optimized macro placement to reduce latency and routing congestion.
- Achieved MCMM timing closure, improving WNS from –0.35 ns to +0.05 ns using buffer optimization, VT swapping, and gate resizing.
- Reduced clock skew by 18% through multi-source CTS and H-tree strategies, improving overall frequency margin.
- Implemented UPF-based low-power architecture using multi-Vt and power-gating techniques, achieving 18% leakage and 12% dynamic power reduction.
- Minimized IR-drop from 7.2% to through strategic decap insertion, optimized strap pitch, and switch-cell placement.
- Improved routing congestion by 22% using macro re-orientation, non-default routing rules (NDRs), and track reservation techniques.
- Resolved 100+ DRC and 20+ LVS violations to achieve a signoff-clean layout compliant with DRC/LVS/EM/DFM guidelines.
- Generated tape-out–ready GDSII compliant with IR/EM reliability and manufacturability requirements.
- Developed TCL/Python automation scripts to streamline placement, STA report extraction, and closure activities, reducing overall flow runtime by approximately 30%
Tools & Technologies:
Synopsys ICC2, PrimeTime, UPF, TCL, Python, Calibre (DRC/LVS/EM), 40 nm
SJB Institute of Technology, Jan 2024 – Feb 2025
Project description: designed and implemented an EEG-based autonomous drone navigation system with a focus on signal processing, control optimization, and system reliability.
Key Responsibilities & Achievements:
- Achieved ~92% navigation accuracy in controlled indoor environments using optimized PID control strategies.
- Improved wireless communication reliability from 70% to 95% through protocol tuning and error mitigation.
- Reduced real-time control latency by 40%, enhancing drone responsiveness and system stability.
- Developed a simulation-based validation workflow due to unavailability of MITSAR-21 EEG hardware, enabling continuous testing and refinement.
- Implemented EEG signal filtering techniques achieving ~85% signal clarity, enabling accurate brain-signal interpretation.
Technologies Used:
ESP32, EEG Interface, Python, MATLAB, PID Control, Wireless Communication Protocols
Leadership And Technical Ownership
RV-SKILLS Center For Emerging Technologies, 04/2025, 09/2025, Bangalore, Karnataka,
- Led final timing and power closure efforts by coordinating across CTS, routing, and sign-off stages under tape-out aligned conditions.
- Drove automation initiative using TCL/Python to accelerate PD flow convergence, improving closure efficiency by 30%.
- Demonstrated decision-making and problem-solving during critical congestion and IR-drop analysis cycles.
SJB Institute of Technology, 01/2024, 01/2025, Bengaluru, Karnataka
- Project Team Lead - BCI Drone Navigation
- Led a team of 4 engineers to develop an EEG-based autonomous drone navigation system with 92% accuracy.
- Managed signal analysis, wireless communication stability, and simulation strategy to ensure project success under hardware limitations.
- Coordinated research documentation, testing phases, and technical presentations.
Languages
English
Proficient (C2)
C2
Hindi
Native
Native
Kannada
Upper Intermediate (B2)
B2
Telugu
Intermediate (B1)
B1
Timeline
ASIC Physical Design of Microprocessor Block (RTL-to-GDSII | 40nm Technology Node)
RV-SKILLS Center For Emerging Technologies
04.2025 - 09.2025
Engineering Intern – LCA Tejas Division
Hindustan Aeronautics Limited (HAL) | Bengaluru
11.2024 - 03.2025
Advanced Diploma - ASIC Design
RV-SKILLS Center For Emerging Technologies
Bachelors of Engineering - Electronics and Communication Engineering
SJB Institute of Technology
Higher Secondary - Science
Kendriya Vidyalaya Hebbal