Summary
Overview
Work History
Education
Skills
Initiatives
Personal Information
Timeline
AdministrativeAssistant

ABHIJIT RAO

Verification Engineer
Bangalore

Summary

7+ years of experience as verification engineer taking up various roles and responsibilities at Qualcomm. 1+ year of internship experience at Intel.

Overview

9
9
years of professional experience

Work History

QDSS lead

Qualcomm India Private Limited
01.2023 - Current
  • Taken up QDSS block and other sub-blocks under debug bubble and leading it Involved in testplanning, discussions with various stakeholders and alignment on deliverables Frequent sync-ups with SVE team to enable them with all deliverables and status presentation to higher management

Integration lead

Qualcomm India Private Limited
1 2016 - 1 2017
  • Started my career as integration lead in the methodology team
  • Ownership of complete integration and ported scripts from SD projects and implemented the same for the first time in BDC projects
  • New methodology for integration (CI flow) developed from scratch and made POR for a project – Complete ownership and implementation Continuous support for all teams to port the scripts and presently all BDC projects are on new integration methodology

QUPSS block ownership and IPA, QSPI lead

Qualcomm India Private Limited
01.2021 - 01.2023
  • IPA and QSPI lead and enabled new resources for these blocks QUPSS block complete ownership taken and didn’t miss any milestones Involved in testplanning, discussions with various stakeholders and alignment on deliverables for all 3 blocks VIP integration for QUPSS (New SNPS VIPs, Q2SPI VIP)

QSPI and IPA block ownership

Qualcomm India Private Limited
01.2017 - 01.2020
  • Moved to Sandiego extension Peripheral team in 2017 Ownership of QSPI block and learnt about verification aspects IPA block ownership along with QSPI was taken and contributed significantly on both SD and BDC projects Many showstopper bugs were caught on IPA and few methodologies were implemented IPA performance methodology won best paper in QBUZZ

Technical Intern

Intel Technology India Pvt limited
01.2015 - 01.2016
  • Part of VPG integration team Involved in many automations and regression cleanup tasks

Education

MSc Tech (ME) (VLSI Design) -

School of Information Sciences, Manipal Academy of Higher Education (MAHE), Manipal

BE (Electronics and Communication) - undefined

K S Institute of Technology (Bangalore, Karnataka)

PUC - undefined

Vijaya Composite PU College, Bangalore, Karnataka

SSLC - undefined

Vijaya High School, Bangalore, Karnataka

Skills

C

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Initiatives

  • Continuous Integration flow, Integration flow for consuming baselines and creating top level baselines – Developed as integration lead for Talos project. New methodology created from scratch which reduces the need of a resource. Eliminates manual work of merging common file changes. All BDC projects have employed same flow.
  • IPA performance methodology, New flow developed in sync with core DV team to extract the IPA vectors and plug them at SoC and run the performance tests. Initially around 2 months of effort was needed to develop performance tests and get results. With the automation, the effort reduced to less than a week and improved the quality of tests. Showstopper bug was caught in Olympic project with the new methodology. Won best paper award at QBUZZ for the new methodology.
  • DAP APB automation, Created new flow for CSR testing of debug registers through DAP. Updated multiple scripts to support DAP testing like QSAM CSR.
  • Coverage grading, To extract minimum number of tests which covers maximum number of functional signal toggles and to add them in Priority testlist. Scripts were developed from scratch to extract information and dump out signal to toggle mapping. Database for all peripheral blocks are created and used as reference. Paper is submitted in Qbuzz - Unraveling the SOC toggle coverage closure hazards with continuous learning approach. Documentation and presentations are prepared for the same and communicated to other teams to try out the same.
  • Fishtail verification, integration script updates and Jenkins, Fishtail execution ownership. Suggestions on improving coverage and followup with respective teams to add new scenarios. Worked on updating multiple integration scripts. Jenkins ownership in BDC and multiple runs were shifted on it.
  • Testbus Automation flow, Testbus signals were manually coded in SV tests and for every project it needed to be changed. Removed manual coding portion and created a DPI to be called in SV test and auto-population of test bus signals.

Personal Information

  • Gender: Male
  • Nationality: Indian

Timeline

QDSS lead

Qualcomm India Private Limited
01.2023 - Current

QUPSS block ownership and IPA, QSPI lead

Qualcomm India Private Limited
01.2021 - 01.2023

QSPI and IPA block ownership

Qualcomm India Private Limited
01.2017 - 01.2020

Technical Intern

Intel Technology India Pvt limited
01.2015 - 01.2016

Integration lead

Qualcomm India Private Limited
1 2016 - 1 2017

MSc Tech (ME) (VLSI Design) -

School of Information Sciences, Manipal Academy of Higher Education (MAHE), Manipal

BE (Electronics and Communication) - undefined

K S Institute of Technology (Bangalore, Karnataka)

PUC - undefined

Vijaya Composite PU College, Bangalore, Karnataka

SSLC - undefined

Vijaya High School, Bangalore, Karnataka
ABHIJIT RAOVerification Engineer