Abhinav Kumar Singh

• Project 1
• timing closure during the ECO phase, resolving critical setup, hold, and transition violations .
• Eliminated DRC and Signal EM violations in high-density routing regions by implementing targeted physical fixes and optimizing wire geometries.
• Mitigated dynamic IR drop issues during late-stage ECOs by strategically inserting decoupling capacitors (decaps) and reinforcing the local power grid structure.
• Analyzed and resolved cross-talk and timing bottlenecks concurrently, ensuring a robust, violation-free design ready for final tape-out sign-off.

• Project 2
• Built custom clock for different clocks having multiple entry points to achieve proper latency .
• Automated pipe addition for compressor and decompressor paths .
• Built custom buffer bank for minimal cross-talk , opitimum delay paths for critical data path between pipe stages.

• Project 1: Technology/Layers 5nm Samsung, 15 metal layer Instance Count 1.1M Hard Macros 1 Tool Innovus, Primetime Role Block Owner This block was highly routing congested due to shape challenges. Completed from netlist to gds2 like Floorplan, Place, CTS, Route, TECO and MECO. Got many antenna violation and PDN issue. Analyzed STA at every stage which helped us to close on time without any hiccups. Fixed Timing DRCs, DRCs, IR related issues.
• Project 2: Technology/Layers 4nm TSMC, 15 metal layer Instance Count 1.8M Hard Macros 10 Tool Primetime, Innovus Role Block Owner Implemented various techniques to resolve shorts hotspots. Area reduction is done to save the overall die area. Performed floorplan, Route, and manual ECO. Did multiple clock push, clock pull to meet critical clock gate timing. Fixed Timing DRCs, DRCs and IR related issues.
• Project 3: Technology/Layers 4nm TSMC, 10 metal layer Instance Count 2.1M Hard Macros 78 Tool Primetime, Innovus Power Domains 6 Role Block Owner This block was highly routing congested due to shape constraints and multiple power domain in it. Maintained proper routing profile and delay profile for feed-through going through different domains in the block. Multiple experiments were done for better skew, Clock ID, and clock power. Setup closure was very critical due to cross-talk and congestion. Leakage recovery was implemented to achieve better power. Fixed Timing DRCs, DRCs and IR related issues.
• Project 4: Technology/Layers 4nm TSMC, 10 metal layer Instance Count 2.3M Hard Macros 152 Tool Primetime, Innovus Role Block Owner This block was highly congested due to high count of logic and hard macros. Multiple Experiments of florplaning was done to have convergence with respect to timing and congestion. Implemented MSCTS using H-Tree to have acceptable latency. Setup and hold closure was very critical due to cross-talk and congestion. Due to lesser metal layers noise fix was critical. Fixed Timing DRCs, DRCs and IR related issues.
• Project 5: Technology/Layers 4nm TSMC, 12 metal layer Instance Count 3.2M Hard Macros 20 Tool Primetime, Innovus Role Block Owner This block was timing critical. Multiple Experiments were done for proper logic and pipe placement to have convergence. Implemented MSCTS using H-Tree to have acceptable latency. Fixed Timing DRCs, DRCs and IR related issues. Implement multiple transport cells requirements for clock feedthrough.
• Project 6: Technology/Layers 3nm TSMC, 10 metal layer Instance Count 4.1M Hard Macros 1310 Tool Primetime, Innovus Power Domains 6 Role Block Owner This block was highly congested due to high count of logic and hard macros. Multiple Experiments of florplaning was done to have convergence with respect to timing and congestion. Implemented MSCTS using H-Tree to have acceptable latency. Fixed Timing DRCs, DRCs and IR related issues. Implement multiple transport cells requirements for clock feedthrough.