Abhisek Sarkar

• Responsible for Understanding ERS
• Responsible for Understanding Architecture & DOS
• Responsible to create Attribute sheet includes test plan, coverage plan, checker, assertions
• Debugged issues related to sequences/functional coverage/assertion implementation and resolved bugs
• Built/deployed full-chip simulation environment versions and ran regression suites
• Project: Custom micro-controller for wireless power transmitter applications (Version 1).

Role: to verify an IP(USBFS) in IP level and in SOC level. (IP ownership)

prepare attribute sheet.

Implementation of sequences, test case, scoreboard

Assertions to check the USBFS functionality.

Implementation of feature-based cover group and its relevant crosses.

Review Specific scenarios with Customer.

Test bench – UVM

Test type – C-UVM

VIP - Synopsys.

Used of suite of Cadence( vmanager , simvision , IMC)

• Project: Custom micro-controller for wireless power transmitter applications

Role: Integration of 2 custom SOC chips

Ran test cases to boot up, Connectivity check through functional test, default value test

Assertions to check the top-level signals, clock, reset

Implementation of feature-based cover group and its relevant crosses with signal exchange between two SOC chips

Top of Waveform presentation to customer

Test bench – UVM

Test type – C-UVM

Used of the suite of Cadence

• Project: Display PMIC

Role: Test cases for different register configuration using SPMI

Analog IC ramping up to a specific voltage level

Implemented checkers to check the different rails in analog and digital domain value is same throughout the simulation while changing the register value

Assertions to check SMPI protocol

Test bench – UVM

Test type – UVM

Used of the suite of Cadence

Project: Soft Start/Down Control Sequence FSMs and VOX Ramp

Role: The soft start controls the power up/down sequence of the analog components for

VOX, is based on FSM dedicated to each VOX and a ramp generator shared with the 4 VOX

Test cases for different VOX’s

Assertions to check the functionality of different VOX’s

Implementation of feature-based cover group and its relevant crosses

Test bench – UVM

Test type – UVM

Used of the suite of Cadence

• Project: CSI2

Integrate the RTL with VIP Write test cases

Implement coverage

Implement scoreboard

Description: The purpose of this CSI-2 controller is a digital core that implements all protocol functions defined in the MIPI CSI-2 specifications ,providing an interface between the system and the MIPI D-PHY/C-PHY, allowing for a communication with a compliant MIPI camera sensor

Test bench – UVM

Test type – UVM

Used of the suite of Aldec Rivera Pro

• Project: XSPI CONTROLLER

Role: Test-Bench Developed in UVM

Coded the Monitor part

The XSPI project defines and describes a standardized into 1s mode, 8d

PROFILE-1.0, 8d PROFILE 2.0

Test bench – UVM

Test type – UVM

Used of the suite of Aldec Rivera Pro

Professional

Training: Trained as ASIC Verification Engineer, VLSIGURU Training Institute, Bangalore.

worked as as DV Engineer,

worked on various IP's(AHB,APB,AXI,XSPI)