Summary
Overview
Work History
Education
Skills
Accomplishments
Tools
Timeline
Generic

Abhishek Joshi

Bengaluru

Summary

Dedicated and results-oriented FPGA Prototyping Engineer with extensive experience in RTL design, High Level Synthesis, FPGA PnR. Seeking to leverage my expertise in a challenging role

Overview

4
4
years of professional experience

Work History

FPGA Prototyping Engineer

Intel
Bengaluru
01.2020 - Current

My Current work include :-

  • Prototyping complex ASIC designs to fit within single or multiple FPGAs, ensuring functional and timing correctness
  • Perform RTL modifications to make design compatible with FPGA platforms
  • Integrate FPGA specific IPs for debug flows and develop RTL glue logic
  • Rewrite/Replace the hard IPs which are part of ASIC with FPGA specific IPs
  • Develop and implement Python scripts for automating routine tasks
  • Develop initial C tests by understanding processor/SoC arch to qualify the FPGA model
  • Optimal placement of IPs within FPGA based on their connectivity with other IPs
  • Delivering timing clean FPGA prototype to customers with maximum runtime capabilities for testing, debugging and error injecting.

Education

B.Tech - Electronics And Communications Engineering

PES University
Bengaluru, KA
05-2020

Skills

  • FPGA Arch Xilinx virtex and ultrascale
  • RTL design and Integration
  • High Level Synthesis in C (Vivado HLS)
  • Hands on experience in FPGA PnR and timing closure
  • AMBA protocol -AXI, AHB and APB
  • In depth understanding - SPI, CAN (both physical and application layer)
  • Interface level understanding - PCle and DDR3
  • Debugging and problem solving
  • Strong in Programming and Automation C/C/Python/tcl

Accomplishments

  • Designed AXI Tracker IP from scratch using transactor IPs. Fully parameterized IP comprised with MMCMs, FIFOs, transactor IPs and glue logic to ease the first level triaging. Also, the presentation of this IP was selected by SNUG( A synopsys tech conference)
  • Developed C scripts for transactor IPs and enabled a seamless flow for SoC validation. This work was appreciated by Software and Firmware teams due to its scalability and performance for developing their content. A paper on this work was accepted by Intel's internal conference ITC.
  • HLS controller design for host <-> FPGA communication over SPI bus. This work helped Software team to develop more stressful scenarios on FUSA compliance Safety IP.
  • Awarded DRA (Divisional Recognition Award) and SRA (Spontaneous Recognition AWARD) twice in the tenure of 4.5 years of service.

Tools

  • VCS - verification and simulations
  • Synopsys Protocompiler - synthesis and inter FPGA routing
  • Synopsys Simplify Premier - Area Analysis
  • Vivado - Intra FPGA Placement and routing
  • Vivado_HLS - C synthesis

Timeline

FPGA Prototyping Engineer

Intel
01.2020 - Current

B.Tech - Electronics And Communications Engineering

PES University

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Abhishek Joshi