Abin Asaf

• Die-to-Die subsystem verification lead for a server SoC.
• Created test plan and verification strategy for the first generation D2D subsystem.
• Spearheaded the development of a versatile die-to-die subsystem testbench, enabling seamless validation across multiple topologies.
• Verified critical blocks using FPV, enhancing early bug detection.
• Achieved company recognition for identifying the highest number of design bugs in a project phase.
• Collaborated effectively with a third-party IP vendor to diagnose and resolve critical IP issues, ensuring project success.
• Partnered with a tool vendor to deploy a coverage optimization feature, resulting in faster verification cycles and reduced regression time.

• Verification lead for IPU IO subsystem and SoC HW security.
• Working on improving verification methodology and quality in group.
• Working to increase formal methodology adoption in group.

Imaging SoC security verification

• Security verification lead.
• Developing SoC security verification plan including IP level.
• Worked on IP level verification of Security Accelerator and One Time Programmable memory.
• Worked on AXI, AHB and APB interfaces.
• Responsible for development of reference model.
• Lead a small team to bring up security flows in SoC.
• Handled verification of multiple IPs simultaneously with the help of a small team
• Supported Post-Si Validation team to bring up security flows.

IPU IO verification

• Verification lead for Gen7 IPU CSI-2 protocol layer.
• Responsible for developing TB architecture and verification plan.
• Developed reference model for end-to-end data checking.
• Support SoC team and die-to-die team for IPU bring up.

IPU Gen6 subsystem verification

• Lead small team of experienced engineers for the verification of Image Processing Unit (IPU) subsystem.
• Responsible for defining test bench architecture and verification plan.
• Successfully completed verification of multiple variants of IPU for different CCG products.

• Responsible for verification of Image Processing Unit(IPU) Input Subsystem for multiple CCG products.
• Responsible for IPU SoC integration verification.
• Responsible for creating test plan, adding new use cases, regression debug and coverage closure.

• Boot firmware and application programming interface verification in an ARM Cortex-M0 based SoC.
• Responsible for creating test plan.
• Verified all functional and security features.