Deep Acharya

Senior Specialist – Physical Design & CAD Automation (Apr 2025 – Present)

• Led RTL-to-GDSII implementation and signoff flows across advanced nodes (7nm, 12nm, 28nm).
• Automated STA, power analysis, and timing closure using Tcl/Python; cut turnaround by 40%.
• Owned floorplanning, CTS, and routing for multiple IPs; drove convergence to clean GDS.

Design Engineer – Physical Design (Jan 2024 – Apr 2025)

• Executed place & route, clock tree synthesis, and IR-drop analysis using Innovus & Fusion Compiler.
• Performed STA and fixed setup/hold violations using ECO and buffer insertion.

Specialist Engineer – IP QA & Signoff (Jun 2023 – Dec 2023)

• Qualified IPs and standard cells across process nodes; automated QA workflows.
• Improved flow coverage and reduced manual errors in signoff flows by 40%.

Graduate Intern – Physical Design QA Automation (Jul 2022 – May 2023)

• Built Python-based automation for delay/power verification.
• Validated libraries for compatibility with advanced node P&R flows.

• Developed and verified digital modulation techniques for satellite communication systems operating at 406 MHz.
• Reduced noise interference and achieved zero data loss using MATLAB simulations.
• Delivered results that enhanced distress management systems' reliability and efficiency.