Adabal Venugopal

• Circuit tuning to meet customer timing targets to meet multiple clock specs in 14A/3nm Libraries.
• Layout co-driven optimizations to create low power/high performance sequential cells for 3nm Libraries
• Circuit Optimizations to find the optimal sizing for single and multi stage combinational cells in 3nm Libraries
• Assessing the Standard Cells Power and performance metrics through PrimeTime to see block level metrics across 3nm/18A/14A Libraries.
• Created Framework from scratch to create a design with all the standard cell library content thereby creating All Cells Design.
• Performed PrimeTime vs SPICE simulations for various timing paths in the All Cells design to assess the PT vs SPICE Correlation & PDK vs PDK in 3nm/18A/14A Libraries.
• High sigma analysis on sequential cells to check for different failures in 3nm Libraries
• Custom Placement automation script is created which produces the most compact area.

Exposure to standard cell characterization Flow and multiple standard cell views