ADARSH VENUGOPAL
Mumbai
Summary
Final-year Electronics and Communication Engineering student (B.Tech, May 2026) with a strong foundationin electronic systems, signal processing, and hardware–software integration.
Experienced in FPGA prototyping, Hardware Acceleration for AI,
embedded systems, and algorithm implementation using Verilog, MATLAB, LabVIEW, and Python. Passionate about developing intelligent sensing and processing systems that blend engineering rigor with innovation.
Education
Bachelor of Technology - Electronics And Communication Engineering
05-2026
- CGPA- 8.54/10
- Minor in: Artificial Intelligence and Machine Learning
Work History
Intern | Information Systems
Nippon Telegraph and Telephone Corporation- Global Data Centers
Mumbai
05.2025 - 06.2025
- Established LLM inference pipelines on AWS EC2 via SageMaker to enhance AI workflows.
- Supported integration of Juniper-based cloud infrastructure for simulation tools in compute validation.
- Contributed to sustainability-focused planning discussions regarding data center operations.
Student Intern | Dept of Technology Risk
Ernst & Young
Mumbai
05.2025 - 05.2025
- Conducted assessments of IT systems and enterprise controls to align with ISO 27001, 27701, NIST CSF 2.0, and GDPR.
- Contributed to compliance evaluations through documentation and checklist methodologies during live audits.
- Acquired experience in technology risk analysis across diverse business environments.
Embedded Systems Project Assistant
SATCARD, IIT-PKD
Palakkad
07.2024 - 08.2024
- Developed a vibration analysis system with a 6-DoF IMU and MCUs like Arduino UNO & Raspberry Pi.
- Calibrated sensors to improve accuracy and reliability.
- Explored sensor fusion for smarter agricultural diagnostics.
Accomplishments
- Tools: Vivado, Vitis, ModelSim, Keil, MATLAB, LabVIEW, AWS Sagemaker
- Languages: Verilog,SystemVerilog, VHDL,Python, MATLAB, C
- Domains: FPGA Deployment, RTL Design & Verification, SoC Design, Hardware Acceleration, DSP, AI & ML
Projects
- FPGA & RTL Design with Verilog: Designed and verified RTL modules (counters, sequence detectors, arbiters) using Verilog and SystemVerilog testbenches. Deployed designs on Basys3 and Pynq FPGAs. Created IPs using Vitis HLS and integrated them with existing IPs to build complete hardware systems.
- FPGA Deep Learning Accelerator: Deployed INT8 quantized ResNet-50 on Xilinx ZCU104 using Vitis AI 3.0; achieved 4.188 ms latency, 30 FPS real-time inference, ~90% Top-1 accuracy, and 24×–70× speedup over ARM Cortex-A53 using DPUCZDX8G (1.2 TOPS, 72.5% efficiency, 3.1 GB/s bandwidth).
- Gunshot Detection System (Ongoing): Designing a real-time gunshot localization system on FPGA using microphone arrays, DoA estimation, and deep learning; submitted to Smart India Hackathon as Project SATARK (Shot Acoustic Tracking and Recognition Kit).
- Voice authentication system: Built a range-restricted voice authentication system with ultrasonic sensing and ML, achieving approximately 99% accuracy
- Fooling a Neural Network: Engineered adversarial attacks using gradient-based methods, degrading the Neural Network's true class prediction by up to 70%
GitHub
https://github.com/AVM-27
Areas Of Interest
- RTL Design, IP Core Development, and High-Level Synthesis
- Hardware–Software Co-Design
- FPGA Prototyping and Hardware Acceleration
- Embedded AI and Cross-Domain Research
Achievements and Volunteering
- University Nominee – Smart India Hackathon (2024)
- Participant – DIR-V FPGA Hackathon, RISC-V Symposium (IIT-M), IIMAPS 2.0 (IISc)
- Qualifier – AI Blueprint of Bharat, Case Study Challenge (IIT-KGP, 2024)
- Runner-Up & Coordinator – AsIEvolve Leadership Program, Rotary
- 4× National Champion – MaRRS Word Chase & Maze of Words
- Member – INCOSE Chapter, Amrita Photography Club
- Volunteer – Outreach campaigns (e.g., Amma’s 70th birthday)
- Active in debates, quizzes, and elocution at college level
Languages
English, Hindi, Tamil
Overview
1
1
year of professional experience