Aditya Chhabra
Senior Staff Application Engineer
New Delhi
Summary
Over 14 years of experience in Emulation and FPGA based prototyping solutions using Cadence and Synopsys platforms. Skilled in bringing up SOCs from scratch on emulation platforms, Linux boot, and performance tuning. Proactively gather customer requirements, deploy solutions, and provide analysis, problem-solving, debugging, and team coordination. Serve as technical owner for multiple customers and projects, dedicated to delivering high-quality results and exceeding expectations in all aspects of work.
Overview
14
14
years of professional experience
2017
2017
years of post-secondary education
Work History
Senior Staff Application Engineer
Synopsys (India) EDA Software Private Limited
06.2023 - Current
- Involved in evaluation, deployment, integration, and training of Synopsys emulation solutions for key customers.
- Extracted out of the box Emulator performance by profiling and tuning for Optimal resource utilization.
- Providing technical guidance on setting up the methodology, tool flow, and new feature deployment.
- Led cross-functional teams to successfully deliver complex projects on time.
- Established positive relationships with customers and other staff members.
Staff Application Engineer
Synopsys (India) Private Limited
02.2021 - 03.2023
- Helping customers bring up their designs successfully on ZEBU ZS5/EP1 emulation platform.
- Debugged the multiple tool issue on customer emulation setup related to performance.
- Extracted out of the box Emulator performance by profiling and tuning for Optimal resource utilization.
- Providing technical guidance on setting up the methodology, tool flow, and new feature deployment.
- Delivered performance tuning training on different Zebu platform solutions.
- Worked on New feature enhancements proposal, and deployment.
- Helping customers bring up ZEBU emulation platform speed adaptor solutions.
Principal Product Validation Engineer
Cadence Design Systems
06.2015 - 02.2021
- Working with the Development team for implementation of Protium Tool features and validation.
- Creation of Test plan development around customer use models and execution, Release sanity testing and Signoff.
- Bring up customer designs in-house with the help of CAE’s.
- Explore the tools developed fully and try to run with the in-house customer designs and find bugs.
- Identify the root cause and get it with the development team.
- Responsible for creation and benchmarking of System level designs for Protium.
- Mentoring and guiding the freshers with different Protium Tool features for validation.
- Debugging Customer designs and SoCs on Simulation, Emulation and FPGA platforms.
Cadence Design Systems
02.2011 - 06.2015
- Creating Verilog based Synthesizable testbenches and Designs for Testbench Acceleration verification.
- Integrating Custom RTL IPs as a Blackbox with the DUT for thorough Validation.
- Interfacing External Hardware Targets with the FPGA Systems for thorough Validation.
- Contribution in the creation and improvement of the infrastructure scripts required for benchmarking.
Education
Master of Engineering - Microelectronics
Birla Institute of Technology And Science
Pilani, IndiaBachelor of Technology - Electrical And Electronics Engineering
Dr.Akhilesh Gupta Institute OfProfessional Studies
New Delhi, India 04.2001 - 01.2008
XIIth - undefined
St. Michaels Sr. Sec. School
Xth - undefined
St. Michaels Sr. Sec. School
Skills
- Verilog design experience
- Shell scripting proficiency
- Data analysis with R
- Proficient in TCL/TK development
- C/C programming
Accomplishments
- GATE 2008-94.36 percentile (All India Rank -853).
- Achieved 1st Position in Chemistry in A.I.S.S.C.E (XIIth) across School.
Practice School
ST Microelectronics Pvt. Ltd., Greater Noida, PLL group, Technology R&D, 01/01/10, 06/30/10, Design and Analysis of a module of Frequency Synthesizer, Frequency Synthesizer is a system which generates variable frequencies. My work was mainly involved in designing a module of frequency synthesizer. I had been given a synthesized 16 phases of the clock (generated by PLL) which were used to generate variable frequencies. The design at every stage was critically analyzed and checked against process corners and temperature drifts., FS Design, Timing Analysis
Disclaimer
I hereby declare that all the information given by me above is correct to the best of my knowledge.
Personal Information
- Father's Name: Late Shri Sushil Chhabra
- Date of Birth: 12/12/86
- Gender: Male
- Nationality: Indian
- Marital Status: Married
Timeline
Senior Staff Application Engineer
Synopsys (India) EDA Software Private Limited
06.2023 - Current
Staff Application Engineer
Synopsys (India) Private Limited
02.2021 - 03.2023
Principal Product Validation Engineer
Cadence Design Systems
06.2015 - 02.2021
Cadence Design Systems
02.2011 - 06.2015
Bachelor of Technology - Electrical And Electronics Engineering
Dr.Akhilesh Gupta Institute OfProfessional Studies
04.2001 - 01.2008
XIIth - undefined
St. Michaels Sr. Sec. School
Xth - undefined
St. Michaels Sr. Sec. School
Master of Engineering - Microelectronics
Birla Institute of Technology And Science
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