AISHWARYA ASHOK PATTANASHETTY

Currently working as Associate - 1 in Capgemini Engineering, Bengaluru from April 2022. 2 year 9 months of industry experience as a Functional Verification Engineer and Formal Verification Engineer in Capgemini Engineering and as an Advanced VLSI Design and Verification trainee in Maven silicon softech pvt.ltd, Bengaluru.

Advanced VLSI Design and Verification, Maven silicon softech pvt ltd, 10/2021 - 04/2022, Design and Verification Trainee

Worked on IP level Functional and Formal verification. Good debugging skills at IP level. Good knowledge in Digital design, Verilog, Systemverilog, SVA, UVM, AMBA AXI, APB, AHB, SPI, I2C, UART, PCIe Protocols, tcl scripting and ABVIPs. Good exposure to JASPER GOLD (formal verification tool ) APPS like FPV, CONNECTIVITY, CSR. Having good debugging skills. Good written & oral communication skills.

1. Project 1: FM8(Falcon Mesa), Intel, 05/2022 - 12/2022, Worked on an IP verification., Running regressions and debugging failures., Loading signal dump in Verdi and debugging failing conditions., Debugged failed testcases., Written tests/sequences based on the requirement., Good knowledge of Cheetah work flow., Questa sim, Synopsys Verdi.

2. Project 2:  DTEG Formal Verification, Intel, 01/2023 - Present, Managed IP formal verification and explored JASPER GOLD TOOL APPS like FPV, CSR, CONNECTIVITY., Worked on 5 IPs verification., Developing the test plan to verify the functionality of the IP., Updating the testplan in Phoenix tool., Written assertions to verify the default values of output signals and registers of IPs, using FPV APP of JG tool and debugged the failures., Written assertions for complex scenarios to verify functionality of IPs using FPV application of JG tool and debugged the failures., Checked the functionality of IPs, by binding the written assertions to rtl using bind file., Done required tcl scripting to run the respectives APPS of Jasper gold, to do CSR, CONNECTIVITY and also FPV (functional as well as default) checks., Configured the config files like design.cfg, gen_filelist.cfg, jasper.cfg files based on the requirements., Recognized RTL bugs, informed designer to do modifications/corrections, which makes IP functionally stable., Recognized the specification mismatch in rtl and HAS, and informed HAS author to update the HAS with respect to rtl., Tunrin of database., Worked on verifiation of port connections of the design using connectivity application of JG tool., Worked on verification of registers of an IP, by setting the entire environment using CSR application of JG tool., In CSR checks, Verified the registers functionality of an IP using ABVIPs like APB3, APB4 ABVIPs., Good knowledge of analyzing and resolving the issues faced while doing the environment setup, and also guided peers on this., Good knowledge of Cheetah work flow., JASPER GOLD FORMAL VERIFICATION TOOL(JG APPS like FPV, CSR, CONNECTIVITY).

I do hereby declare that all the above details are true to the best of my knowledge & belief.

                                                                                                  Aishwarya Ashok Pattanashetty