Ajay Kashyap Pasumarti
DFT Engineer
Bengaluru
Summary
With 4.9 years of experience as a DFT engineer, extensively worked on DFT insertion (EDT/OCC/SCAN/BSCAN), ATPG and pattern validation. My quick learning capabilities have helped me facilitate.
Overview
7
7
years of professional experience
3
3
Languages
Work History
Application Engineer
Siemens EDA
10.2023 - Current
- Worked on various DFT Solutions provide aby Siemens and Helped the customers with design/custom-DFT-insertion scripts review. Also Unblocked customers by solving pre-tape out issues w.r.t DFT.
- Generated target accounts sales objectives, opportunities and projection reports to prioritize work.
- Visited clients to determine feasibility, analyze requirements and provide solution suggestions.
- Provided exceptional customer support, addressing client concerns and providing timely resolutions to technical issues.
- Exhibited strong technical aptitude and application expertise resulting in optimized performance, continuous improvement recommendations and product innovation.
DFT Engineer
Intel
03.2022 - 09.2023
- Established strong working relationships with clients through exceptional communication skills, fostering trust and collaboration.
- Achieved successful project outcomes by maintaining accurate documentation and meeting strict deadlines.
- Developed positive working relationships with stakeholders to effectively coordinate work activities.
- Presented technical findings to stakeholders, ensuring clear understanding of project status and goals.
Senior Design Engineer
Insemi Technology
Bengaluru
09.2020 - 03.2022
Design Engineer
Truechip Solutions
Bengaluru
09.2018 - 06.2020
Education
PG-D - VLSI
CDAC-ACTS
Pune, India06.2018
B.Tech - Electronics And Communications Engineering
ECE
Kamala Institute Of Technology & Science 04.2001 -
Skills
Good understanding of fault models, ATPG, fault economics, scan insertion techniques, BIST (Logic, Memory), JTAG (Boundary Scan), Compression
SCAN, ATPG and Simulation Failure debugging
Knowledge on DFT principles scan insertion, controllability/observability, ATPG for Stuck- at faults, Transition faults, TDF, Fault models
Mentor’s Tessent for DFT-RTL-Insertion/ATPG
undefinedInterests
Chess, Battalion
Hands on Scripting
- Shell-scripting
- TCL-scripting (basics)
Timeline
Application Engineer
Siemens EDA
10.2023 - Current
DFT Engineer
Intel
03.2022 - 09.2023
Senior Design Engineer
Insemi Technology
09.2020 - 03.2022
Design Engineer
Truechip Solutions
09.2018 - 06.2020
B.Tech - Electronics And Communications Engineering
ECE
04.2001 -
PG-D - VLSI
CDAC-ACTS
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