
Postgraduate in VLSI and Embedded Systems with over 7 years of industry experience in FPGA-based RTL design, testing, and debugging. Strong expertise in digital design, embedded systems, research-driven problem solving, and hardware validation.
HDL:
Verilog, VHDL, SystemVerilog
EDA Tools:
ModelSim, Xilinx ISE, Vivado, Libero SoC, HDL Designer
Core Knowledge:
RTL Coding, IP/RTL Integration, Libero Design Flow, Vivado Design Flow, Linux, IP/SoC-Based Design Methodology
Protocols & Interfaces:
SPI, I2C, AXI4, HDMI (Intermediate), DisplayPort (Design Level)
Programming & Scripting Languages:
C (Intermediate), Perl (Basic), TCL Scripting (Vivado & Libero)
Other Skills:
Team Coordination, Cross-Functional Collaboration