Summary
Overview
Work History
Education
Skills
Certification
ADDITIONAL INFORMATION
Timeline
Generic

ALAHARI VIJAY SARATHY

PHYSICAL DESIGN ENGINEER
Bangalore

Summary

Experienced Physical Design Engineer with 7+ years of proven expertise in physical implementation and verification across advanced technology nodes (5nm to 18A). Strong track record working with leading clients like Intel, NVIDIA, and Marvell, handling complex, timing-critical, and macro-dominant blocks. Adept in debugging congestion, timing, and IR/EM issues. Actively involved in knowledge sharing, documentation, and mentoring team members.

Overview

8
8
years of professional experience
1
1
Certification
1
1
Language

Work History

Physical Design Engineer

Tech Mahindra
01.2024 - Current
  • Executed PnR implementation and ECO changes for timing and routing fixes.
  • Resolved critical IR, EM, LVS, and DRC violations on advanced node designs.
  • Led multiple cell and metal-only ECOs with over 300 re-routes and 80 cell insertions.
  • Provided support to peers and shared best-known methods for new scenarios.
  • Client: Intel

Physical Design Engineer

Quest Global
01.2021 - 01.2024
  • NVIDIA – 5nm (TSMC), 2.849 GHz
  • Managed macro-dominant blocks with high congestion and critical timing paths.
  • Optimized macro placement and resolved congestion via bound/path groupings.
  • Addressed IR/EM issues and implemented critical DRC fixes.
  • Actively assisted team members in debugging complex issues.
  • Marvell – 14nm
  • Handled multiple blocks, performed clock transition fixes and congestion resolution.
  • Executed timing ECOs to achieve timing closure.
  • Led initiatives for high-quality routing and DRC cleanup.
  • Clients: NVIDIA, Marvell

Physical Design Engineer

Altran Technologies
01.2018 - 01.2021
  • Delivered physical design implementation across various technology nodes.
  • Resolved critical re-routing, DRC, IR, and LVS challenges.
  • Played a key role in training initiatives and authored a user guide for faster onboarding.
  • Client: Intel – 7nm, 10nm, 14nm, 18A

Education

Bachelor of Engineering - ECE

SCSVMV University (Deemed)

Skills

  • Physical Design: Floorplanning, Placement, CTS, Routing, Optimization
  • Timing Closure: Setup/Hold, IR/EM analysis, CTS methodologies
  • Physical Verification: DRC, LVS, Metal-only and Cell-based ECOs
  • Technology Nodes: 5nm, 7nm, 10nm, 14nm, 18A
  • Tools: Innovus, ICC, PrimeTime, Calibre, Workbench
  • Scripting: TCL, Unix/Linux
  • Team Collaboration & Mentorship
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Certification

Physical Design Course – QSOCS Technologies Pvt Ltd, Bangalore

ADDITIONAL INFORMATION

  • Date of Birth: 1995-07-23
  • Address: 891, 2nd Cross, 7th Main, 5th Block, BEL Layout, Vidyaranyapura, Bangalore – 560097

Timeline

Physical Design Engineer

Tech Mahindra
01.2024 - Current

Physical Design Engineer

Quest Global
01.2021 - 01.2024

Physical Design Engineer

Altran Technologies
01.2018 - 01.2021

Bachelor of Engineering - ECE

SCSVMV University (Deemed)

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ALAHARI VIJAY SARATHYPHYSICAL DESIGN ENGINEER