AMIREDDY SIVANAGIREDDY
Bengaluru
Summary
Highly motivated VLSI graduate with strong knowledge of Physical Design (RTL to GDSII) and Static Timing Analysis (STA). Hands-on exposure to ASIC flow, floorplanning, placement, clock tree synthesis, routing, and timing closure. Seeking an opportunity to contribute technical expertise and analytical skills to a semiconductor organization while continuing to grow in Physical Design and STA.
Overview
1
1
Certification
Education
Bachelor’s degree - Electronics and communication Engineering
MVR College of Engineering and Technology
01.2025
Intermediate (10+2 class) - undefined
Kamala – Junior College
01.2021
Secondary School (10th class) - undefined
Sri Chaitanya High School
01.2019
Skills
- Physical Design: RTL to GDSII Flow, Synthesis, Floorplanning, Placement, CTS, Routing, ECO, DRC/LVS, Power Optimization
- Static Timing Analysis (STA): Setup/Hold Analysis, Clock Skew, Jitter, OCV, Multi-Corner Multi-Mode (MCMM) Timing Closure, SDC Constraint Writing
- Digital Design: Combinational Logic Design, Sequential Logic Design
- Operating System: Linux, Windows
- Text Editors: GVIM, Notepad, TCL
- Tools and Technologies: Synopsys Design Compiler, ICC2, PrimeTime, Cadence Innovus, Mentor Graphics Calibre
- MS Office: Good working knowledge of Excel and Microsoft Word
- Other Skills: ASIC Flow, TCL, Communication Skills
Certification
Physical Design & STA – VLSI Guru Institute, Bengaluru
Timeline
Intermediate (10+2 class) - undefined
Kamala – Junior College
Secondary School (10th class) - undefined
Sri Chaitanya High School
Bachelor’s degree - Electronics and communication Engineering
MVR College of Engineering and Technology
Disclaimer
I hereby declare that the information provided above is true to the best of my knowledge. As a fresher, I am eager to apply my skills in Physical Design and STA, adapt quickly to new technologies, and contribute to the growth and success of the organization.
PERSONALITY TRAITS
- Adaptability
- Positive Attitude
- Time Management
Training
- Physical Design & STA Training : VLSIGURU INSTITUTE Jun 2025 – present
- Hands-on experience with ASIC implementation flow: RTL → Synthesis → Floorplan → Placement → CTS → Routing → Signoff.
- Good knowledge in Static Timing Analysis (STA) concepts such as setup/hold, timing arcs, constraints, clock skew, OCV, derates, and path analysis.
- Practical understanding of power analysis, congestion analysis, and design rule checks (DRC/LVS).
- Strong understanding of digital design concepts.
- Familiar with complete ASIC design flow and proficient in using GVIM for efficient code editing.
- Fundamental knowledge of programming language such as Linux.