Summary
Overview
Work History
Education
Skills
Accomplishments
Certification
Timeline
Generic

Amit Lalchand Waghmare

Nagpur,Maharashtra

Summary

Total experience of 8 YEARS as FPGA IP Design engineer. 4 Years of experience as FPGA IP DESIGN ENGINNER AT INTEL/Altera. 1 Year 6 months of experience as Engineer-II and 4 months of experience as Senior Engineer-I at Microchip technologies Hyderabad. 2 Years 2 month of experience as Research scientist at SAMEER, IIT Bombay.

Overview

8
8
years of professional experience
1
1
Certification

Work History

FPGA IP DESIGN ENGINEER

ALTERA
09.2021 - Current
  • I handled end to end IP development, Start form creating Functional Document, Test plan creation, IP development, regtest generation
  • Developed AXI clock crossing bridge IP and added CSR support for the Avalon CCB IP
  • Worked on IP development of AXI TIMEOUT BRIDGE IP
  • Worked on Simulation model for FP8 NOC.
  • Worked on Development of NOC Bridge IP's like Initiator, Target and clock control.
  • Handled BCM testing for Falcon Park 8 NOC on agilex 7 devices.
  • Worked on validation of NOC after Power ON of Fp8.
  • Good Knowledge on TCL and perl Scripting.
  • AXI BRIDGE IP development for the INterconnect
  • Filed Patent for the hard IP simulation.
  • Have good working knowledge of VCS, MSIM, RIVERA and Xcelium simulation tool for Verilog and vhdl.
  • worked on linting and CDC test for IPs with the F-max improvement.

Senior Engineer I

Microchip Technologies Hyderabad
09.2019 - 09.2021
  • Worked on RTL-IP development of MIPI receiver, HDMI transmitter and receiver IP with audio support.
  • Worked on CNN models like Tiny-yolov2, Tiny-yolov3, mobilenetv2, resnet-50 and Posenet. Performing data extraction, Normalization, and quantization on CNN models in python.
  • Deploying CNN model on CNN engine of FPGA and perform postprocessing on FPGA using RTL coding and MI-V (softcore processor) using embedded C.
  • Good understanding of the Complete FPGA design flow and implementation using Microsemi Libero tool and Soft-console.
  • Experienced with Microsemi FPGA Boards such as Polarfire (Video kit), smart fusion boards.
  • Experience on Parallel Camera interface and configuration.
  • Good knowledge on python NumPy, TensorFlow, keras libraries.

Research Scientist

Society for Applied Microwave Electronics Engineering & Research
07.2017 - 09.2019
  • Hands on experience in RTL design, Behavioral design, Implementation, Verification, Synthesis, Simulation and Test of Digital Systems.
  • Good understanding of the Complete FPGA design flow and implementation using Xilinx Vivado, SDK.
  • Experienced with Evaluation general purpose FPGA Boards such as Artix series, Kintex Series FPGA Board, Zynq SOC Boards.
  • Experience in board-level interface such as SPI, I2C.
  • Experience in working with high-speed serial ADC/DAC with serial and parallel interfaces.

Education

Master of Engineering - Digital System

Maharashtra Institute of Technology
PUNE
01.2016

Bachelor of Engineering - Electronics & Telecommunication

Babasaheb Naik College Of Engineering
PUSAD
01.2013

Diploma of Engineering - Electronics & Telecommunication

Govt. Polytechnic
GADCHIROLI
01.2010

Secondary School Certificate -

MAHATMA GANDHI HIGH SCHOOL
Armori, India
01.2007

Skills

  • Programming Languages: VHDL, Verilog, MATLAB, LabVIEW, C/C, Python, OpenCV
  • Hardware Platforms: Xilinx ZYNQ ZC702, ZC706, ZYBO Kintex KC705, Nexys 4 DDR, Spartan6, Arduino uno/Mega, NI MyDaq
  • Softwares/Tools: QUARTUS, VCS, MODELSIM Xilinx Vivado, Xilinx ISE, Mathworks MATLAB, LabVIEW, Microsoft Visual Studio C
  • ADC/DAC: ADS5263, ADS5294, DAC34H84, DAC AD9122, DAC AD5791
  • Interface Protocols: SPI, I2C, UART, SERDES
  • Operating System: Windows 7, Windows 81, Windows 10, Ubuntu

Accomplishments

  • IEEE PAPER: Published paper on “Water Velocity Measurement Using Contact and Non- Contact Type Sensor”, International conference on Communication, Control, and Intelligent System (CCIS -2015) IEEE sponsored conference at GLA University, MATHURA, INDIA
  • PATENT : Novel method of elaborating and simulating Hard IPs that cannot be instantiated within
    customer facing IPs

Certification

  • VSD- Static Timing Analysis - I and VSD- Static Timing Analysis - II on Udemy. The certificate earned in May 2018.
  • System Verilog Beginner: Write Your First Design and Test Bench Module on Udemy. The certificate earned in June 2018.
  • System Verilog Function Coverage Language/Methodology/apps on Udemy. The certificate earned on July 2018.
  • Attended the workshop on ARDUINO BOT conducted by Robosoft systems at the IIT-Bombay
  • Attended the workshop on LabVIEW Programming conducted by Measurement's & sensor Division at VIT University, Vellore.

Timeline

FPGA IP DESIGN ENGINEER

ALTERA
09.2021 - Current

Senior Engineer I

Microchip Technologies Hyderabad
09.2019 - 09.2021

Research Scientist

Society for Applied Microwave Electronics Engineering & Research
07.2017 - 09.2019

Master of Engineering - Digital System

Maharashtra Institute of Technology

Bachelor of Engineering - Electronics & Telecommunication

Babasaheb Naik College Of Engineering

Diploma of Engineering - Electronics & Telecommunication

Govt. Polytechnic

Secondary School Certificate -

MAHATMA GANDHI HIGH SCHOOL

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