Open To Work
ANIKET SINGH
NOIDA
Summary
Accomplished Physical Design Engineer with expertise in flow setup and debugging at Qualcomm India. Proven track record in achieving timing closure and optimizing floor plans, while effectively managing multiple projects. Strong attention to detail and excellent communication skills drive successful outcomes in high-stakes environments.
Overview
4
4
years of professional experience
1
1
Certification
Work History
Physical Design Engineer
Qualcomm India Private Limited
NOIDA
05.2024 - Current
- Contributed to flagship DDR designs for compute segment and upgraded version 2.0.
- Developed video subsystem for next-generation Qualcomm SOC.
- Created efficient floor plans maximizing area, power, and performance goals.
- Managed multiple design projects concurrently, prioritizing tasks to meet deadlines and budget.
Physical Design Engineer
Synapse Techno Design Innovations Private Limited
Bangalore
07.2022 - 05.2024
- Converged design toward closures across all project aspects.
- Executed debugging and scripting for full APR.
- Implemented complete netlist to GDS-II flow process.
Physical Design Engineer
MediaTek
Bangalore
12.2022 - 12.2023
- Setup initial flow for APR for multiple blocks, reshaped the blocks according to area requirements for each major netlist change
- Closed its timing and stabilized it for future milestone
- Took the design towards closure at every major milestone
- Made the CTS recipe stable with multiple CTS experiments to reduce the skew and ultimately the slack
- Worked on both blocks parallel for some time and now also actively contributing for the team after ramping down from the project
Physical Design Engineer
MediaTek
Bangalore
06.2023 - 10.2023
- Instance count: 0.7 M | Macro count: 21 | Block size: 1151 X 805 microns (RECT) | PD: 1 AON, 2 switchable It has 1 big Analog macro took care of the special measures that were required for it.
- Closed timing at each milestone
- Cleaned PV and IRHC and EPIC for each milestone till tape-out among which IR cleanup being critical most of the times
- Other efforts like making TCIC compliant shapes while adhering to all FPQ checks requirements and cleaning violations in a sustainable manner
M. Tech.
NIT Rourkela
Rourkela
09.2021 - 05.2022
- A transimpedance amplifier-based pulse oximeter which determines the SpO2 and heart rate of the person
- SpO2 and heart-rate are being measured and compared with a commercial pulse oximeter (ZM-700-01). The accuracy for SpO2 and heart-rate is to be found ± 4 % and ± 2 bpm respectively, with the operating ranges of 70 - 100 % for SpO2 and 25 - 300 bpm for heart rate
- Then, the measured values are displayed on a 3.5-inch TFT LCD and also sent over a secure internet web server so that one can monitor the values on his/her mobile or desktop
- Further, a prototype PCB is also designed and a prototype has been fabricated
Education
M. tech - Electronics and Instrumentation Engineering
NIT Rourkela
Rourkela, Odisha05.2022
B. Tech - Electronics and Communication Engineering
BIET Jhansi
Jhansi, UP08.2020
Skills
- Flow setup and debugging
- Scripting and automation
- Coordination and multi-block management
- PV cleanup and IR fixing
- Exploration of new techniques
- Floor planning and CTS strategies
- Placement optimization
- Timing closure techniques
- DDR and video subsystem designs
- Effective communication skills
- Attention to detail
Websites
Certification
- Innovus Implementation System (Block) v21.1 Exam, Cadence Design Systems, 07/13/2022
- Basic Static Timing Analysis v2.0 Exam, Cadence Design Systems, 07/13/2022
- IC Compiler II: Block Level Implementation Jump-start, Synopsys, 07/28/2022
- Prime Power: Jumpstart, Synopsys, 07/26/2022
- Prime Time: Jumpstart, Synopsys, 07/25/2022
- Basic Level Telecom and Business Field, BSNL Jhansi, 06/29/2019
Languages
- English
- Hindi
Publications
Real-time Voltage Mode Pulse Oximetry System, 2022 IEEE19th India Council International Conference (INDICON), Kochi, India, 02/2022, Aniket Singh, S. K. Kar, V. K. Sinha, https://ieeexplore.ieee.org/document/10039890
Projects
DDR subsystem - 3nm ffe SOC, 05/13/2024, 09/20/2024, Qualcomm, NOIDA, Noida, Uttar Pradesh, Instance count: 1.5 M, Macro count: 84, Block size: 1300 X 600 microns (RECT), Overview: 2 home nodes, placed in a dumble shaped FP with routes going in between through the neck, Learned systematic buffering for 2000 FT, taking care of the criticality such as NDR and routing stats and cell types as required (clock FT or critical data FT), Highly timing critical block and sensitive block, till the last, Major challenges: FP, CTS and timing closure DDR subsystem 2.0 - 3nm ffe SOC, 11/04/2024, 03/18/2025, Qualcomm, NOIDA, Noida, Uttar Pradesh, This was the enhanced version of the previous project, made to support higher frequencies than its previous gen, Faced timing challenges in this also as it was supposed to close on higher frequency, Same efforts as done for its previous version Video subsystem - 4nm ffp SOC, 04/28/2025, 06/04/2025, Qualcomm, NOIDA, Noida, Uttar Pradesh, Instance count: 3.1 M, Macro count: 215, Block size: 2000 X 700 microns (RECT), Overview: First of its kind SOC in 4nm (architecture wise), a flattened whole subsystem was assigned to me which generally has 3 sub blocks, small PD team of me and my manager only, Major challenges: FP: Congestion heavy block, took around 10 FP to converge initially Video subsystem - 2nm ffe SOC, 05/26/2025, Present, Qualcomm, NOIDA, Noida, Uttar Pradesh, Block 1: Instance count: 3.12 M | Macro count: 215 | Block size: 977 X 1012 microns (RECT), Block 2: Instance count: 1.41 M | Macro count: 40 | Block size: 393 X 414 microns, Overview: These are 2 sub blocks of Video subsystem, apart from its own logic, Block 1 consists of another sub block which introduces hierarchical challenges in the design 5G - 4nm ff SOC [Low Power], 06/01/2023, 10/04/2023, MediaTek, Bangalore, Bangalore, Karnataka, INDIA, Instance count: 0.7 M, Macro count: 21, Block size: 1151 X 805 microns (RECT), Closed timing at each milestone 5G - 7nm ff BSC SOC, 12/01/2022, 12/15/2023, MediaTek, Bangalore, Bangalore, Karnataka, INDIA, Setup initial flow for APR for multiple blocks, reshaped the blocks according to area requirements for each major netlist change Real-time Voltage Mode Pulse Oximetry System, 09/01/2021, 05/01/2022, NIT Rourkela, A transimpedance amplifier-based pulse oximeter which determines the SpO2 and heart rate of the person
Passions
- Electronics technologies
- Gaming
- Photography
Work Preference
Job Search Status
Open to workWork Type
Full TimeLocation Preference
On-SiteSalary Range
₹199000/yr - ₹200000/yrTimeline
Physical Design Engineer
Qualcomm India Private Limited
05.2024 - Current
Physical Design Engineer
MediaTek
06.2023 - 10.2023
Physical Design Engineer
MediaTek
12.2022 - 12.2023
Physical Design Engineer
Synapse Techno Design Innovations Private Limited
07.2022 - 05.2024
M. Tech.
NIT Rourkela
09.2021 - 05.2022
M. tech - Electronics and Instrumentation Engineering
NIT Rourkela
B. Tech - Electronics and Communication Engineering
BIET Jhansi