Summary
Overview
Work History
Education
Skills
Accomplishments
Interests
Timeline
Generic

ANUBHAV

Physical Design Engineer
Bangalore

Summary

To explore and build a long term career in the field of VLSI by utilizing and applying my skills in a goal oriented manner for the organization and also looking forward to expand my level of expertise, learning new skills and to be continuously updated with new concepts and innovative ideas.

Overview

4
4
years of professional experience
8
8
years of post-secondary education
2
2
Languages

Work History

Senior Engineer

QUALCOMM India Pvt Ltd
Bangalore
07.2019 - Current
  • So far worked on around 12 projects in an span of 4 years.
  • Worked on cutting-edge technologies like 7nm, 5nm, 4nm and 3nm.
  • Responsible for DDR subsystem level and Block level Floorplanning to achieve better utilization.
  • Responsible for Block level Place & Route activities on high performance challenging design and coming up with the recipes and methodology for better Power, Performance and Area.
  • Responsible for timing closure of high performance designs.
  • Responsible for all non-timing closure of the block (FV, CLP, PDN and PV)
  • Worked in both flat and hierarchical designs.

Education

M.Tech - Telecommunication System Engineering

IIT Kharagpur
Kharagpur, West Bengal
05.2017 - 06.2019

B.Tech - Electronics And Communications Engineering

IET Lucknow
Lucknow
04.2013 - 05.2017

Intermediate -

T.R.M Public School
Modinagar, Uttar Pradesh
03.2011 - 03.2012

SSC -

T.R.M Public School
Modiangar,Uttar Pradesh
03.2009 - 03.2010

Skills

    Focused

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Accomplishments

    AIR- 621 in GATE-2017.

Interests

Computer Games

Volleyball

Gym Workout

Timeline

Senior Engineer

QUALCOMM India Pvt Ltd
07.2019 - Current

M.Tech - Telecommunication System Engineering

IIT Kharagpur
05.2017 - 06.2019

B.Tech - Electronics And Communications Engineering

IET Lucknow
04.2013 - 05.2017

Intermediate -

T.R.M Public School
03.2011 - 03.2012

SSC -

T.R.M Public School
03.2009 - 03.2010

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ANUBHAV Physical Design Engineer