ANURAG KAR
Pune
Summary
Highly skilled engineer with a decade of experience spanning embedded systems to RISC-V microprocessor development. As an Engineering Manager at Espressif, played a pivotal role in launching its first line of RISC-V microprocessors, demonstrating exceptional technical expertise and leadership. Passionate about advancing computing technologies and driving innovation.
Overview
11
11
years of professional experience
Work History
Engineering Manager - Digital Design
Espressif Systems
01.2022 - Current
- Led critical modules of a 32-bit 5-stage RISC-V core, successfully taped out for mid-range edge IoT devices with AI inference capabilities
- Architected and developed a 5-stage accelerator integrated parallel to the core pipeline, optimized for AI/DSP algorithms using custom ISA with hundreds of complex SIMD and fused instructions
- Enhanced PPA by optimizing critical control and data paths, ensuring timing closure through advanced methodologies
- Upgraded LSU datapath for wide SIMD operations and misaligned transactions, while tweaking MMU architecture for efficient translation of page-boundary operations
- Developed a trace logger module closely integrated with an out-of-order 12-stage superscalar CPU, enabling effective debug and verification
- Automated binary encoding generation for custom ISA with complex SIMD instructions
- Collaborated with toolchain and application teams to finalize instruction formats for custom ISA
- Explored various branch prediction schemes, improving Coremark performance
- Directed the development of Supervisor privilege mode and platform-level interrupt controller integration
- Mentored engineers in designing SIMD arithmetic units with optimal resource sharing and pipelining
- Built a tool to identify nodes and connections in production netlists for ECO purposes
- Awarded ESP-Maverick Award Q3 2023 for outstanding contributions to digital design and team leadership
Digital Design Engineer
Espressif Systems
08.2019 - 12.2021
- Owned key modules of a 32-bit 4-stage RISC-V core, successfully integrated into ESP32 product lines targeting the IoT market
- Enhanced control unit and LSU to support atomic instructions and improved branch prediction unit, boosting Coremark by 20%
- Designed and implemented Machine/User privilege separation and associated CSRs
- Developed a hardware trigger module for debug features like breakpoints and watchpoints
- Built a custom interrupt controller and integrated local timer/software interrupt sources for SoC requirements
- Created a comprehensive C-based test suite to verify RISC-V core features and compliance
- Ported open-source benchmarking suites for CPU performance evaluation
- Resolved critical RTL bugs and implemented FPU testing by integrating TestFloat with SystemVerilog using DPI-C
Embedded Software Engineer
Espressif Systems
06.2018 - 07.2019
- Developed a low-footprint, highly customizable open-source HTTP server component for ESP-IDF
- Authored reference applications showcasing file serving, asynchronous parsing, and error handling
- Built a secure Wi-Fi provisioning framework for IoT products based on ESP32
- Enhanced native pthread implementation to support AFR-required attributes
- Debugged and resolved detached thread issues causing runtime exceptions
- Awarded 'Bring it On!' Best Employee Award 2019 for exceptional contributions to software development
Research and Development Engineer
Quazar Technologies Pvt Ltd
08.2014 - 11.2017
- Designed and prototyped mixed-signal systems for precision scientific instruments
- Developed firmware for AVR microcontrollers interfacing with AD/DA converters
- Conducted full board bring-up and resolved hardware design flaws
- Modeled and optimized design parameters through mathematical computations and physical simulations
- Analyzed experimental data to validate theoretical models
- Managed production targets, supervised unit testing, and ensured product line sustenance
Education
Integrated Master of Science - Physics
Indian Institute of Technology Kanpur
Kanpur, UP07.2014
Skills
- Verilog / SystemVerilog
- C / C / Python / Assembly
- RISC-V (RV32/RV64) / SIMD
- Computer Architecture
- Single Issue / Dual Issue / Superscalar Pipelines
- PPA Optimization / Low-Power Design
- Timing Closure / ECO / C Verification
- AXI / AHB / APB Protocols
- Synopsys DC / VCS / Verdi
- Vivado / Verilator
Timeline
Engineering Manager - Digital Design
Espressif Systems
01.2022 - Current
Digital Design Engineer
Espressif Systems
08.2019 - 12.2021
Embedded Software Engineer
Espressif Systems
06.2018 - 07.2019
Research and Development Engineer
Quazar Technologies Pvt Ltd
08.2014 - 11.2017
Integrated Master of Science - Physics
Indian Institute of Technology Kanpur
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