Aravind Kota

Highly-motivated employee with desire to take on new challenges. Strong worth ethic, adaptability and exceptional interpersonal skills. Adept at working effectively unsupervised and quickly mastering new skills.

Has experience in Cadence virtuoso, Voltus pi (EMIR), Spectre, Calibre (DRC,LVS,ANTENNA). Experience in multiple tapeouts in multiple technologies from 180nm to 3nm with different foundries.

Designed a circuit & layout for 32 different clock frequencies generated with 5 control input pins & 1 output in 22fdsoi with pre to post layout verification with multi corner signoff (Silicon Proven).

• Full chip DRC, LVS, DFM, ERC in 4nm, 12nm, 22fdsoi, 130nm, 180nm.
• Custom IP level designs of drc, lvs, erc in 3nm, 12nm.

• Layout design using 12nm Soc Chip implementation - fully hierarchical implementation using genus, innovus. Checking physical verification (DRC,LVS,ANTENNA) of blocks and gives feedback to the physical design team.
• SRAM & Cache memories with N3 technology - Creating a Custom memory layout of leaf cells, sub-blocks, blocks. Creating a floorplan, powerplan, placement & routing. Checking DRC, LVS, ERC for the memories & checking the IR drop then improving it by adding power stripes.
• SRAM & Cache memories with N3E technology - Creating a Custom memory layout of leaf cells, sub-blocks, blocks. Creating a floorplan, powerplan, placement & routing. Checking DRC, LVS, ERC for the memories & checking the IR drop then improving it by adding power stripes.
• Soc Chip hardening with 12nm technology - Fully hierarchical implementation using ICC2. Responsible for all sub blocks and chip level checking physical verification & giving feedback to the physical design team.
• RISC-V Cores hardening - Multiple RISC -V cores (single core, multiple cores, multiple architectures) physical design implementation & meeting PPA analysis with mixed vt, targeting ranges to 2GHz at 12nm. Checking the physical verification of a block.
• Hierarchical block implementation using hybrid technology - Creating a custom layout of manual clock tree for balancing of all sinks with wire balancing.
• Hierarchical Block of Chip implementation with N4 technology - Target frequency of 1GHz. Checking voltus ir/em analysis , physical verification.
• Designed a layout of tspc flop with optimized area in 12nm for bitcoin project - Reduced the overall area chip area by 15 %. Created multiple sub blocks with DRC, LVS, ERC.

PROJECT LEAD :

• Hierarchical Block implementation using Hybrid PDK (130-90nm) - Target frequency of 800 MHz with continuous feedback to RTL team for upgrading RTL to reach goals. For achieving frequency & balancing clock latency between all sinks. Created a manual placement with tcl script & giving constraints for routing. Reviewing an analog layout of sub blocks of LVDS RX, BGR, LVCMOS. Placing a 19 LVDS RX & 5 LVCMOS in chip level & connecting it to the Pads.

I hereby declare that the above information is correct to the best of my knowledge and that I will be held responsible for any deviation from them at a later stage.