Aravind Kota

• Block-level implementation of physical design in 12 nm using Innovus. Placing custom pin placement with different widths and shielding. Meet the IO skew, STA (1 GHz), EMIR, and Physical Verification.
• SoC-level implementation of creating bumps, guidelines for I/O placement, and analog blocks in 16nm using Innovus. Full chip-level physical verification. Chip size is 16 mm x 20 mm.

Physical design

• SoC-level implementation of creating bumps, guidelines for I/O placement, and analog blocks in 12nm using Innovus. Full chip-level physical verification. Implemented the clock mesh structure to reduce the clock skew between the synchronous blocks. Checking the skew through spectral analysis. Frequency is 1 GHz. Chip size is 12 mm x 16 mm.
• SoC-level implementation of RTL to GDS using Genus and Innovus in 130-90 nm (hybrid). Hierarchical implementation of blocks, and meet the STA and IO requirements for chip-level integration. Created a wire-dominated custom clock tree to reduce clock skew, and custom pin placement to connect easily to the analog block. Physical verification for block and chip level.
• Block-level implementation of the RISC-V processor (single core, multi cores, multiple architectures) from RTL to GDS in 12 nm using Genus and Innovus. Physical design implementation and meeting the PPA with mixed VT; the targeted frequency is 2 GHz.

Layout Design:

• Implementation of custom blocks (Array, Lio, Gio, decoder, Gctrl, Lctrl) in SRAM, I-cache, and D-cache memories. Creating leaf cells, floor planning, power planning, EMIR, and physical verification in 3nm and 5nm.
• Designed a custom layout of TSPC flop with optimized area in 12nm, which will reduce overall chip area utilization by 15%.

Custom IP's (Design to Gds):

• Implemented a ring oscillator block of circuit design and layout, which will generate 32 different frequencies with 5-bit input signals and 1 output signal in 22FDSOI technology. Created a circuit, layout design, physical verification, LEF, LIB, pre-layout, and post-layout simulations.

Circuit Design:

• Worked as a datapath designer in 12 nm. Creating blocks that will perform mathematical operations and optimize the design. Using the Tempus tool (STA) for checking the critical path timing violation.
• Custom SRAM circuit design in 3 nm. Design blocks like a lion, decoder, Control, Array. Doing the simulations of the design and resolving any margin-failing paths. Optimizing the design to achieve the PPAL with Vt changes, different architectures.
• Worked as a project lead for Analog Blocks in 130-90 nm. Monitoring blocks like BGR, LVDS, CMOS RX, and TX receivers created by the team and giving them feedback to optimize the design of area requirements.