Summary
Overview
Work History
Education
Skills
ATE TEST ENGINEER (POST SILICON VALIDATION)
Languages
Hobbies and Interests
Websites
Timeline
Generic
ARAVINDH SINGH

ARAVINDH SINGH

Electronicity Phase 2, Bangalore

Summary

ATE TEST ENGINEER (POST SILICON VALIDATION)

ATE Test Development Engineer with 7+ years of experience in IC Testing involving Test Plan Creation, Test Program Development, Data Analysis, Yield improvement, Debug of the device, Test Time Reduction and Release to customer across diverse semiconductor products.My commitment to innovation has led me to explore emerging technologies within semiconductor design and testing, allowing me to devise cost-effective solutions with minimal iterations in the debugging process. Eager to contribute my expertise to a dynamic engineering team, I am poised to leverage my skills and experience to transform complex problems into efficient, scalable solutions.

Overview

8
8
years of professional experience

Work History

Test Program Development Engineer

INTEL
Bangalore
12.2019 - Current
  • SOC - CLIENT PRODUCTS
  • Proficient in SoC/IP validation, debug & characterization of analog, high-speed digital (HSIO) and Mixed signal IP such as SICC,DICC,CEP,LVR PLL, PCIE interface and HBM in semiconductor development life cycle.
  • Developed test plans, test solutions for digital SOC’s on HDMT platform
  • Test plan preparation for all IP's based on Designer Input.
  • Pre silicon verification of patterns, Pattern conversion and Test Program development for all test cases
  • Char data analysis and characterization gap debug with the help of cross functional teams.
  • PCIE subsystem test plan development and test case bring up
  • Yield improvements Debug and Test Time reduction
  • ATE vs System correlation and guard band implementation.
  • Data crunching and analysis using Microsoft Excel and JMP tool.
  • Debugged and analyzed issues with design team on further actions based on test experiments.
  • Preparing test procedure / methodology for test specifications and making time frame for execution.

Test Program Development Engineer

INTEL
Bangalore
12.2019 - Current
  • TestChip - Foundary Services
  • Test program development for intel custom based eASIC products for 5G/Automobile/Avionic/Networking applications
  • In this team I worked on couple of products as owner for end-to-end development
  • Responsibilities start from designing load board until fixing the yield issues in HVM sites
  • Engineered advanced load board designs and performed meticulous schematic verification
  • PCIE subsystem test plan development and test case bring up
  • Yield improvements Debug and Test Time reduction

ATE Test Development Engineer

TESSOLVE SEMICONDUCTORS
Bangalore
12.2016 - 12.2019
  • Worked on Test plan to Production release on various semiconductor products WLAN 5GHZ FRONT-END IC, STEREO AUDIO CODEC IC and CAN TRANSCEIVER IC.
  • Executed multisite FT conversion from VLCT to Advantest V93000. Developed Test Program for Load Board Diagnostics and Test Parameters for calculating ADC/DAC Test Specifications such as Offset, GERR, SNR, THD
  • Converted Test Program for WLAN 5GHZ FRONT-END IC from SPEA to 93K with in very short time frame which includes program development from scratch, onsite debug and release activities in 12 weeks. Release activities includes Spike- check, 5K loop run, MSC (multisite correlation), TTR(Test Time Reduction), Code review and STR(sample test request 34 wafers) , Improved the probe yield.
  • Developed wafer and final test program for various CAN TREANSCEIVERs, debugged, reduced the test time with in the expected range and released in SPEA C372MX tester platform.
  • Led feasibility studies and resource optimization to boost multisite testing efficiency
  • Streamlined and optimized across-temperature testing procedures, significantly reducing test cycle times.

Education

MTECH in - Microelectronics With 7.9 CGPA

BITS
Pilani, India
02-2022

BACHELOR OF ENGINEERING - in ECE With 7.3 CGPA

Anna University, Chennai
TamilNadu, India
04-2015

HIGH SCHOOL EDUCATION -

Bharat Matric Higher Secondary School
Krishnagiri, Tamilnadu

Skills

  • HDMT
  • SPEAMX320
  • C, C
  • TEST PROGRAM DEVELOPMENT
  • TEST TIME REDUCTION
  • QUALITY ASSURANCE
  • CHARACTERIZATION
  • DATA ANALYSIS
  • INTEGRATION
  • YIELD IMPROVEMENT
  • PRESENTATIONS
  • LINUX
  • COMMUNICATIONS
  • ROOT CAUSE ANALYSIS
  • DEBUGGING
  • RESOURCE ALLOCATION
  • CALIBRATION
  • ADVANTEST V93000

ATE TEST ENGINEER (POST SILICON VALIDATION)

Nationality: Indian

Languages

  • ENGLISH
  • HINDI
  • TAMIL
  • KANNADA

Hobbies and Interests

  • CRICKET
  • TENNIS
  • TABLE TENNIS
  • BADMINTON

Websites

Timeline

Test Program Development Engineer

INTEL
12.2019 - Current

Test Program Development Engineer

INTEL
12.2019 - Current

ATE Test Development Engineer

TESSOLVE SEMICONDUCTORS
12.2016 - 12.2019

MTECH in - Microelectronics With 7.9 CGPA

BITS

BACHELOR OF ENGINEERING - in ECE With 7.3 CGPA

Anna University, Chennai

HIGH SCHOOL EDUCATION -

Bharat Matric Higher Secondary School

Similar Profiles

CREATE PROFILE
ARAVINDH SINGH