Summary
Overview
Work History
Education
Skills
Volunteering And Interests
Phone
Publications
Leadership And Achievements
Timeline
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Sanjana Chopra

Staff Engineer - Digital Design, Analog Devices
Delhi

Summary

Accomplished RTL Design Engineer with 8+ years of experience in digital design, top-level integration, and system-on-chip (SoC) development for complex mixed-signal products. Proven ability to drive architecture, RTL implementation, synthesis, and post-silicon validation. Known for leadership in multi-disciplinary teams and consistent success in high-performance, low-power ASIC and SoC designs. Passionate about high-impact system design, debug, and optimization.

Overview

9
9
years of professional experience
2016
2016
years of post-secondary education

Work History

Staff Engineer - Digital Design

Analog Devices
05.2023 - Current
  • Led top-level SoC integration and coordinated RTL handoff across firmware, DV, and backend teams.
  • Designed and implemented a custom RTL sequencer for digital beamforming chips.
  • Developed an Ethernet-to-datapath buffering logic, leveraging deep understanding of network protocol timing and data integrity.

Senior Design Engineer

Analog Devices
04.2020 - 05.2023
  • Architected and implemented Rx-path RTL for a transceiver SoC.
  • Owned RTL design and verification of FIR/IIR filters and signal generation blocks.
  • Conducted full-chip gate-level simulations for power and timing closure; performed debug using Tempus Toolkit.
  • Post-silicon responsibilities included SPI-based testing, root-cause analysis of ADC-related spurs, and delivering >70dB noise reduction.

Design Engineer

Analog Devices
08.2016 - 04.2020
  • Designed fractional delay filter IP and contributed to front-end signal chain RTL.
  • Developed assertions and static timing constraints for capture mode and at-speed testing.
  • Automated report analysis through scripting, accelerating verification closure cycles.

Education

M.Tech - Electrical Engineering (Signal Processing, Communication, Networks)

Indian Institute of Technology Kanpur

B.Tech - Electronics & Communication Engineering

Indira Gandhi Institute of Technology, IP University

Skills

  • RTL Design (Verilog, SystemVerilog)

  • Digital Signal Processing Systems

  • SoC Integration & Verification

  • Static Timing Analysis (STA)

  • Post-Silicon Validation

  • Clock Domain Crossing (CDC) Handling

  • Gate-level Simulations

  • Power Analysis

  • Synthesis & Formal Verification

  • Protocols: Ethernet, SPI

  • Tools: Tempus Toolkit, MATLAB

  • Scripting: Perl, Shell

  • Languages: C, C

Volunteering And Interests

CSR: Teaching & school development (2017-2019), Sketching, reading fiction, classical dance

Phone

+91, 9650052470

Publications

  • "Not Just Another Sequencer Design!" - ADI GTC 2024 (Boston), India Tech Conf 2023
  • "Sparse Doubly Selective Channel Estimation...", IEEE Transactions on Communication, 2020
  • "ACO, Its Modification and Variants", IJCTT, 2014

Leadership And Achievements

  • ADI 'Ten Under Ten' Award 2021
  • Head, Young Professional Network, ADI Bangalore (2021-2022); launched 4+ engagement initiatives
  • Spot awards for project tapeouts in 2019, 2021, 2023, 2025
  • Mentored interns and interviewed full-time hires (2019-present)
  • Led cultural initiatives for ADI Day 2019

Timeline

Staff Engineer - Digital Design

Analog Devices
05.2023 - Current

Senior Design Engineer

Analog Devices
04.2020 - 05.2023

Design Engineer

Analog Devices
08.2016 - 04.2020

B.Tech - Electronics & Communication Engineering

Indira Gandhi Institute of Technology, IP University

M.Tech - Electrical Engineering (Signal Processing, Communication, Networks)

Indian Institute of Technology Kanpur

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Sanjana ChopraStaff Engineer - Digital Design, Analog Devices