ARJUN SAVANT
Bangalore
Summary
Dynamic verification manager with extensive experience at Samsung Semiconductor, leading a team to enhance SoC verification quality. Expert in UVM and power-aware verification, fostering collaboration and mentoring engineers. Achieved significant improvements in architecture robustness and project delivery timelines, while driving innovative solutions in complex multi-processor environments.
Overview
8
8
years of professional experience
Work History
SOC Verification for ALIVE Block - Manager
Samsung Semiconductor
Bangalore
03.2025 - Current
- Manage 4 engineers verifying the Always-On Block by leading verification strategy, ensuring quality, resolving issues, setting measurable performance goals, and contributing ideas for IEEE publications.
- Foster team growth by mentoring, motivating, and guiding career development and skill enhancement.
- Resolve conflicts, promote collaboration across teams, and ensure timely, high-quality project delivery.
SOC Verification for ALIVE Block -IC
Samsung Semiconductor
Bangalore
09.2021 - Current
- Contributed to end-to-end SoC verification across Mobile, Automotive, and AI platforms.
- Verified boot flow and ALIVE (AON) subsystem, including Cortex-M23 firmware for power modes, TZPC, and DRAM initialization.
- Developed system-level and negative scenarios, uncovering spec gaps and improving architecture robustness.
- Enabled Cortex-M55 bring-up in DV environment and supported complex multi-processor/SMP scenarios.
- Built and enhanced UVM-based environments (Processor VIPs, pseudo-SMP); optimized simulation runtime with SNR ,interrupt table mapping techniques.
- Executed UPF-based power-aware verification, validating power domains, isolation, retention, and state transitions.
- Debugged functional and low-power issues using waveform tools and collaborated closely with design/firmware teams.
- Implemented ROMCODE coverage to verify SoC reset release sequence and ensured coverage of firmware controlling power management activities.
- Developed static and dynamic checkers (Python/SV) for interrupts, IPC, ECC and UPF retention strategies.
Design Verification Engineer
Scaledge
06.2018 - 09.2021
- Serializer Block/IP Verification (Jan 2021 - Aug 2021)
- Client: Western Digital
- Serializer design specification understanding.
- Developed Test cases for newly added features and debugged failures, verified.
- Found numerous bugs in RTL. Filed JIRA for the RTL bugs finding.
- Developed Checker for verifying design correctness. Functional Coverage & Code Coverage and analysis to achieve coverage goal.
- IBC Agent development / IBC IP Verification (June 2020 - Jan 2021)
- Client: Micron
- Development of IBC Agent: 1) Base Layer 2) TX Agent 3) RX Agent 4) IBC sequence 5) IBC Configuration.
- Integrating and verifying RX Agent in MsgGen test bench. Integrating and verifying TX Agent in MsgRcv and MsgQ test bench.
- Integrated and added support in IBC agent as per the requirements in DMA, UFS, XTCM, SAM, RM, RDC, CLM, NFC etc. IP's.
- Developing a testcase for underflow features in MsgQ module (MsgQ IP verification).
- System tag/RefQAllocators IP Verification in Flash Controller (Jan 2019 - June 2020)
- Client: Micron
- Specification understanding of System tag of Flash controller SOC.
- Developed Test cases for newly added features and debugged failures, verified.
- Found numerous bugs in RTL. Filed JIRA for the RTL bugs finding.
- Developed Checker for verifying design correctness. Functional Coverage & Code Coverage and analysis to achieve coverage goal.
- Gained foundational knowledge in ASIC design and verification principles.
- Formerly known as PerfectVips
Education
Master of Technology - VLSI Design & Signal Processing
Vishwakarma Government Engineering College
Ahmedabad01-2018
Bachelor of Engineering - Electronics and Communication
Babaria Institute of Technology
Vadodara01-2015
Skills
SoC Verification Methodologies
- UVM (SystemVerilog)
- Constrained Random Verification (CRV)
- Coverage-Driven Verification (CDV)
- SystemVerilog Assertions (SVA)
- UPF & Power-Aware Verification
- System Verilog, Verilog, C/C, Python
- Cadence: Xcelium Indago
- Synopsys: VCS Verdi
- Siemens EDA (Mentor): QuestaSim
- AMBA: AXI, AHB, APB
- Linux
- Waveform Analysis
- RTL Debugging
- Post-Silicon Debug
- Tarmac Debug (ARM Cortex-M)
Accomplishments
- Employee of the Month Award for exhibiting Samsung core value "People First" as part of new managerial role in SSIR.
- Employee of the Month Award in SSIR for successful bring up of Cortex-M55 Processor in Volume Exynos SOC for the first time.
Spot Award in SSIR to enhance the verification scope and find a corner case bug which led to RTL Spin-Off in Volume Exynos SOC. - Rising Star Award for successful completion of Systag Allocator IP Verification from Client Team. Paramount achievement Award at PerfectVIPs for Systag Allocator IP Verification.
Timeline
SOC Verification for ALIVE Block - Manager
Samsung Semiconductor
03.2025 - Current
SOC Verification for ALIVE Block -IC
Samsung Semiconductor
09.2021 - Current
Design Verification Engineer
Scaledge
06.2018 - 09.2021
Master of Technology - VLSI Design & Signal Processing
Vishwakarma Government Engineering College
Bachelor of Engineering - Electronics and Communication
Babaria Institute of Technology