ARUN SRIVASTHAVA

I am a Physical Design Engineer with 4.2 years of experience who likes to handle complex situations and work with challenges in achieving the best possible outcomes for self and organizational growth. An interested being in research and development for improving luxury and safety for global life.

• Technology: 7nm, 5nm.
• Implementation Tools: Fusion Compiler, Prime Time, Innovus.

Project Description:

Working on Fusion compiler tool on 7nm Technology with frequency 1GHz, handling 2 blocks (paraccqatssmb & paraccqatssmg) and taking care from PnR and all signoff checks. Having a mscro count of 106 & 45 and instance count of 2M.

· Seen Intel Health Check violations related to lego compliances and fixed those.

·  Working on timing violations by enabling CCD options to optimize data paths.

Project Description:

Worked on innovus, genus, caliber tool on 7nm technology with frequency 1GHz, handled a block (census) and taken care of all signoff checks. Having an instance count of 0.1M

· Worked on complete PNR & Synthesis.

· Tried experiments by setOptMode, and setPlaceMode to reduce area and power consumption in the design.

· Seen utilization jumps from CTS to Routing because of hold optimization. So enabled useful skew and tried to reduce latency to bring utilization under control.

· Fixed Opens, shorts and Antenna Violations and LVS Clean.

· Fixing DRCs like Min Spacing, Min area, Cut-to-Cut spacing violations.

Project 3

Client: INTEL

Project Description:

Worked on INTEL project with cheetah 2 flow on 7nm technology with frequency 5GHz, handled 2 blocks (pargpioS0 & pargpiod2d) from PnR and taken care of all signoff checks. Having a macro count of 100 and instance count of 0.5M.

· Take care of partition from Eco stage and cleaned violations.

· Written manual Eco’s and fixed setup and Hold violations.

· Fixed Tran and cap issues by adding buffers and splitting fanout.

· Fixed DRCs like Min Spacing, Min area, Cut-to-Cut spacing.

· Seen Level Shifter and Isolation strategy missing violation in VCLP.

· Applied timing exceptions like false paths for few paths and addressed some half cycle paths.

Project 4 Client: INTEL

Worked on the INTEL project with RLS flow (GTKIT) on 5nm technology with frequency 3GHz blocks (gtaxfsouthrccap2, gtaxfsouthrccap3, gtaxfnorthrccap2) and taking care of all signoff checks.

· Seen huge congestion & density issues in few locations of core area and macro channel because of less available routing tracks within congestion regions. So, I have applied Cell padding (Keepout for aoi&oai cells) & also created partial placement blockages with 70 %. After I have seen less congestion and less density in the whole design.

· Worked on block level Timing fixes, added shielding for victim nets for preventing the crosstalk and timing violations.

· Created skew groups to reduce the skew issues and try to balance the clock by set_clock_balancing_points to reduce latency and skew in the design.

· Done clock push & clock pull for critical paths to close block level timing.

· I have seen few violations on clock slowslope (clock tran) and slowslope violations (data tran), fixed those violations by adding buffer or by upsizing the buffer. Addressed some other violations like illegal cells, ClockCellsOndatapath, MaxCap.

· Seen SI path violations and done cloning (flop duplication) at Eco stage and fixed those paths.

· I have rolled timing Eco’s for fixing top-level timing violations at signoffstage.

Project 5 Client: INTEL

Worked INTEL project with cheetah flow on INTEL 7nm technology with frequency of 0.909GHz and handled a block (vinfraucenter) with a macro count of 11. Handled from ECO and taken care of all signoffs checks and tape out.

· Take care of partition from Eco stage and cleaned violations.

· Got Few interface and internal timing & caliber violations feedback from Sub-system. So, have rolled and addressed those violations through PT Eco, and fixed manually left over violations.

· Fixed Tran and cap issues by adding buffers and splitting fanout.

· Fixed Opens, shorts and Antenna Violations and LVS Clean.

Project 6

Client: INTEL

Worked on INTEL project with cheetah flow with INTEL 7nm technology closing block from synthesis to sign off testing. Worked on a block (parcpmssmf) with frequency of 1.16GHz with a macro count of 36 and instance count of 0.5M.

· Worked on floorplan to make sure better placement. All macros I have placed based on macro grouping/hierarchy based.

· Created the group paths, applied timing effort app options to bring setup under control at placement stage. And applied bounds for few hierarchies to bring logic close to each other and bringing setup under control.

· Applied placement blockage at notch to avoid congestion and applied keep-out margin for some hierarchy to reduce congestion. And applied congestion effort app option to reduce congestion overall design.

· Some paths having high data path depth and observed crosstalk violation on those and few path nets were routing in lower layers and promoted them to higher layers. By these experiments, timing brought under control.

· Rolled out PT Eco and fixed Setup, Hold, Tran, Cap violations at Eco phase. And written manually eco to fix the rest of the violations.

· Fixed dynamic ir fixes by downsizing the cell, by changing the cell locations and by inserting the De-caps in the design.

· Fixed Opens, shorts and Antenna Violations and LVS Clean.