Summary
Overview
Work History
Education
Skills
Accomplishments
Timeline
Generic

Arunit Raj

Hyderabad

Summary

Results-driven Silicon Design Engineer with expertise in low-power verification for complex SoCs, using C++, SV, and UVM-based environments. Involved in SoC-level verification of complex SoCs that are embedded into the client profile's mainstream APUs. Known for strong problem-solving skills, attention to detail, and effective collaboration across teams, contributing to successful project outcomes.

Overview

3
3
years of professional experience

Work History

Silicon Design Engineer 2

AMD India Pvt. Ltd.
Hyderabad
09.2023 - Current

Project 1: STX Halo

  • Performed the low-power verification for ACP, NBIO, ISP, and HUBS IPs.
  • Presented the test plan of the above IPs, covering all the cross scenarios.
  • Debugged functional and UPF-related issues encountered in the assigned IPs.
  • Created an automated local regression setup to launch and monitor runs, and report early failures.

Project 2: Medusa 1

  • Verified DLDO-based low power designs.
  • Verified IP-level callouts for SoC to cover all different paths of SoC on the assigned IPs.
  • Integrated IP-level stimulus to SoC-level for cross-scenario verifications.
  • Verified advanced power features of AMD for power-saving mechanisms.
  • Dealt with retention-based memories with PG enabled at SoC-level simulations.

Project 3: Medusa DT

  • Performed the low-power verification for the Core, System Scenarios, and USB IPs.
  • I worked on NLP XOVER analysis on SoC-level simulations. Make sure the Reset vs. Clamp mismatches are reported to the respective IP team, and get them fixed.
  • Developed an NLP bind checker with VCS-provided UPF flow for XOVER reporting.

Co-Op Intern

AMD India Pvt. Ltd.
Hyderabad
07.2022 - 12.2022
  • I have undergone SoC architecture flow and PG scenarios with respect to static and dynamic PG for various IPs.
  • Creating and maintaining regression tests for multiple IPs in an SoC.
  • Helped in initial debugs and created internal pages for tracking all data (includes Test Plan, JIRAs and callouts, Regressions)

Education

M Tech. - VLSI Design (ECE)

National Institute of Technology, Surathkal
Karnataka
07-2023

Bachelor of Engineering - Electrical, Electronics And Communications Engineering

Lakshmi Narain College of Technology, Bhopal
Madhya Pradesh
09-2020

Class 10th And 12th -

Saraswati Vidya Mandir, Bhagalpur
Bihar
05-2016

Skills

  • Low-power verification
  • Verilog
  • SystemVerilog
  • AXI protocol
  • VCS
  • Debugging skills
  • UPF
  • OOP's basic

Accomplishments

  • Secured AIR 881 in GATE 2021
  • Contributed to AATC (AMD Asia Technical Conference) by writing a poster (Title: "Automated Cross-Over Verification Techniques for Enhancing Low Power Design Integrity"

Timeline

Silicon Design Engineer 2

AMD India Pvt. Ltd.
09.2023 - Current

Co-Op Intern

AMD India Pvt. Ltd.
07.2022 - 12.2022

M Tech. - VLSI Design (ECE)

National Institute of Technology, Surathkal

Bachelor of Engineering - Electrical, Electronics And Communications Engineering

Lakshmi Narain College of Technology, Bhopal

Class 10th And 12th -

Saraswati Vidya Mandir, Bhagalpur
Arunit Raj