ASHFAQ SHAIK

Motivated Rookie Digital Design Engineer with a strong desire to learn from industry experts and immerse myself in the dynamic field of Semiconductor Design. Proficient in effectively managing multiple priorities and completing tasks promptly with a positive mindset. Demonstrated ability to be organized, dependable, and willing to assume additional responsibilities to support team achievements.

• Secured Top band and received appreciation certificate for taking a seminar on Dynatrace monitoring tool in TCS
• Secured Full Fee-waiver for Graduation.
• Secured 99.15% percentile in JEE Mains (2015) & Secured 97.24% percentile in GATE (2022)
• Qualified PET & BEC

• Proposed a methodology to detect Hardware Trojans using logic testing methods from TrustHub benchmarks.
• Focused on fault testing-based Hardware Trojan detection methods.
• Implemented MERO (Multiple Excitation of Rare Occurrences) and PODEM ATPG for further hardware Trojan detection.

• Developed and implemented an Automatic Test Pattern Generation (ATPG) algorithm using Path-Oriented Decision Making (PODEM) for efficient test vector generation in digital circuits.
• Integrated this with Fault Equivalence and SCOAP projects to detect Stuck-At-Faults in a combinational circuit.

• Implemented the MERO algorithm, widely used in the industry for testing ICs for Hardware Trojans.
• Programmed test vectors to trigger rare nodes multiple times to detect Trojan activities.
• Achieved results using ISCAS85 and ISCAS89 benchmarks, with Trojan-infected circuits from TrustHub.

• Designed an 8-bit counter using Verilog, verified with Xcelium and a testbench.
• Synthesized a netlist with DFT using Genus, generated test patterns using Modus, and created a GDS2 file using Innovus.
• Performed timing analysis using Tempus tool.

• Designed a fault equivalence analysis tool for VLSI testing to identify and cluster equivalent faults, optimizing test pattern generation.
• Demonstrated problem-solving skills by converting a netlist into a data structure and implementing fault equivalence concepts in code.

• Designed and implemented the Scandia Controllability Observability Analysis Program (SCOAP) to assess the controllability and observability of nets.
• Converted netlist data into structured code to determine how difficult it is to control or observe net values at primary outputs.

• Designed nine instructions for arithmetic, logical, and decision-making computations.
• Implemented three types of MIPS processors: single-cycle, multi-cycle, and pipeline.
• Observed parameters like CPI and throughput for performance evaluation.

• Designed a bit-level multiplier using Modified Booth encoding and Radix-4 Booth algorithm to reduce addition operations.

• Designed a 4-bit Ripple Carry Adder using Verilog and simulated the design in Vivado.
• Generated a bitstream file, programmed a BASYS3 FPGA, and verified functionality.

• Designed an asynchronous FIFO using VHDL based on the concept of handshaking, to facilitate communication between processes running at different speeds.

• Implemented various VHDL-based designs, including:Ripple Carry Adder
  Binary to Gray Counter and vice-versa
  FSM-based basic keyboard and vending machine