Ashish Chilukoti

Design Verification Engineer with 3.4 years of experience specializing in IP and SOC level verification.

Project 1: DDR5 Controller Verification [IP  Level]

Client : Cadence Design Systems

Verification of DDR5 memory controller using VIPCAT and updating VIPs as per  latest specifications.

• Running different set of regressions.
• Debugging, understanding of the failures (controller, TB, DFI or SIMPHY) and fixing if it is TB/SIMPHY issue.
• Updating of TB according to the latest specification updates.

Project 2: Luxor-COSS(Connectivity Subsystem)  [SOC Level] 

Client : NXP semiconductors

Verification of LPI2C and I3C IPs blocks.

• Understanding the block specifications.
• Understood SoC flow. Worked on data flow, interrupt and DMA testcases.
• Worked on I3C VIP integration.
• Worked on coverage closure (toggle).

Project 3: Development of verification plans for an AI  tool.

Client : SemiLabs 

Created verification plans including assumptions, assertions and coverage for  multiple IPs.

• Understanding the design document.
• Creating verification plans, which include writing assumptions, assertions and coverage information.
• Created verifications plans for I2C master, I2C slave, SPI master, SPI slave, I2S transmitter, I2S receiver, UART.

Project 4: I2C master IP core verification  [IP Level]

Client : Inhouse

Verification of I2C Master IP Core with APB interface commands and testbench  development.

• Understanding protocol specification.
• Preparing test plan. Building testbench and testcases.
• Passing various testcases and analyzing the output.
• Analyzing the functional coverage.

Project 5: Video Frame Buffer [IP Level]

Client : Lattice semiconductors

Verification of Video Frame Buffer IP Core supporting up to 4K x 4K image sizes  and multiple video formats.

• Created the test plan, coverage plan.
• Developed AXI Stream RX, AXI stream TX Verilog modules for transferring the data, AXI4 lite master Verilog module for configuring registers.

Project 6:

A) Debayer [IP Level]

Client : Lattice semiconductors

Verification and debugging of Debayer IP including regression debugging and  checker development.

• Regression debugging for Debayer 1.2.0.
• Updated the test case for Debayer 1.2.1
• . Added the support to enable the Debayer 1.2.1.
• Developed the checkers for error scenarios.
• Found the RTL related bugs and resolved.

B)Automatic White Balance[IP Level]

  Verification of AWB IP including regression debugging and checker development. 

• Regression debugging for AWB 1.2.0.
• Updated the test case for AWB 1.2.1.
• Added the support to enable the AWB 1.2.1.
• Added the checkers for error scenarios.

C)Color correction matrix [IP Level]

  Verification of CCM IP including regression debugging and checker development.

• Regression debugging for CCM 1.2.0.
• Updated the test case for CCM 1.2.1.
• Added the support to enable the CCM 1.2.1.
• Added the checkers for error scenarios.

Project 7: Advanced Extensible Bus (AXI) 

Slave  Verification of AMBA AXI protocol including testbench development and  debugging.

• Understanding the specifications.
• Extracted the AXI features and created features list from specifications.
• Developed the test-bench components of sequence, monitor, agent and test cases.
• Debugging the errors.

I hereby declare that the information furnished above is true to the best of my knowledge. 

Place: Bangalore                                                                                                                                         (Chilukoti Ashish)