Ashish Pandey

Demonstrated success in gray, white and black box testing. Write and understand test cases, create test plans and identifying use cases. Comprehensive understanding of full software development lifecycle.

Highly-motivated employee with desire to take on new challenges. Strong work ethic, adaptability, and exceptional interpersonal skills. Adept at working effectively unsupervised and quickly mastering new skills.

Responsible and motivated student ready to apply education in the workplace. Offers excellent technical abilities with software and applications, ability to handle challenging work, and excellent time management skills.

• I2S PROTOCOL VIPs (company project), Developed Verification IPs (VIPs) for the I2S protocol, utilized in digital audio communication between integrated circuits., Implemented System Verilog modules for generating and verifying the Bit clock line, WS line, and SDA line signals., Verified the protocol's functionality in transmitter and receiver modes, ensuring correct signal generation and reception.
• I2C PROTOCOL VIPs (company project), Created System Verilog Verification IPs (VIPs) for the I2C protocol, facilitating data transfers over a two-wire interface comprising SCL and SDA lines., Verified data transfer speeds across various modes, adhering to timing specifications for Standard Mode, Fast Mode, and High-Speed Mode., Validated compatibility with different devices, ensuring correct data transmission rates and bidirectional communication.
• AHB PROTOCOL (company project), Developed System Verilog Verification IPs (VIPs) for the AMBA AHB bus interface, optimized for high-performance synthesizable designs., Verified the interface between components such as Managers, interconnects, and Subordinates using System Verilog assertions and functional coverage., Supported multi-Manager designs, ensuring proper arbitration and routing signals between different Managers and Subordinates.
• APB PROTOCOL (company project), Implemented System Verilog Verification IPs (VIPs) for the Advanced Peripheral Bus (APB), a low-cost interface in the AMBA Protocol family., Verified signal transitions synchronized with the clock, simplifying integration into System Verilog Test benches., Ensured compatibility with low-bandwidth peripherals, providing efficient data transfer without the need for high-performance protocols like AXI.

Expectation from Job: To be able to learn and succeed in an environment of growth in terms of technical and managerial, a job which provides me satisfaction and self-development and helps me to achieve personal as well as organization goals.

Career wise foreseeing the growth in which domain: SoC verification engineer, VLSI, Embedded System etc.

Goal with respect to our career after 5 years where you want to be: To become expert in domain and get a position where I can manage projects as a leader.

• READING BOOKS
• PLAYING CRICKET

• DATA ANALYTICS IN PYTHON AT INFOLABZ