ASHISH TANWAR

Dynamic hardware engineering professional with experience at UST Global, where I developed a Transformer-based model enhancing chip design efficiency. Proficient in VLSI design and Python programming, I excel in collaborative environments, driving innovative solutions that optimize performance and power management in semiconductor circuits. Recognized for outstanding project contributions.

Machine learning acceleration on FPGA: Kria Kv260, ZCU 104 - Hardware, Software Co-Design

Implemented machine-learning algorithm acceleration on Xilinx ZCU 104 and Kria KV 260 FPGAs using VITIS-AI, and developed a custom application for the Kria KV 260 Vision AI development kit for object detection using the YOLOv3 model

8-bit PISO Shift Register using Cadence Virtuoso, VLSI Design

Designed an 8-bit parallel-in, serial-out shift register based on D flip-flops. Input is loaded as a 2-bit serial output in each cycle. Also, I developed a design methodology that supports the conversion of this design to construct an N-bit shifter circuit. The next input will be loaded when all bits have been extracted from the output

RISC-ISA-based 6-stage pipeline processor – Advanced VLSI Architecture

Designed a pipelined RISC-ISA having six stages (Instruction Fetch, Instruction Decode, Register Read, Execute, Memory Access, and Write Back) and nineteen instructions in Verilog
Implemented data forwarding and branch prediction techniques to remove data and control hazard issues in pipelined datapath design flow
Simulated the RTL design and tested it using a custom testbench in Intel Quartus Prime

Implementation of AXI Lite Interface – VLSI Test and Testability

Designed an AXI Lite module in Verilog to handle write, read, and response transactions, adhering to AXI-Lite protocol specifications

Verified the design by developing a constrained random testbench in System Verilog to simulate and validate functionality. Used Xilinx  Vivado for simulation, debugging, and waveform analysis

GATE 2021 Electrical Engineering, Rank 562

GATE 2021 Instrumentation Engineering, Rank 447

Verilog for an FPGA Engineer with the Xilinx Vivado Design Suite, Udemy

SystemVerilog Fundamentals, Udemy

• Emerged as the runner-up in the intra-hostel tournament conducted by BITS Pilani in the table tennis tournament
• Emerged as the runner-up in the intra-hostel tournament conducted by BITS Pilani in the mixed table tennis tournament

Role: Programm Organizer, Cause: Social Servicesl Services

I organized a blood donation camp as a member of the NSS unit during my undergraduate course