Skilled Pre-Silicon Verification Engineer with 15.5+ years of robust background in verification domain, delivering innovative solutions to complex technical challenges. Expertise in designing scalable and secure architectures that align with business objectives. Demonstrated strong analytical skills and collaborative approach to drive successful project outcomes.
Languages/Methodologies : SV, UVM, OVM, C, C, VHDL, Verilog, Perl, Python, Ruby
Protocols : AXI, AHB, APB, ACE, UART, SPI, I2C, USB(Basics), Bluetooth standards
Architectures : ARM , Intel
Simulators : VCS, Questasim, Verdi, IES
Emulators : Z1, Zebu and Veloce
Version Control Systems : GIT, Clearcase, Designsync, SVN, CVS
JIRA, HSD, Github, Github copilot
SOC level, Subsystem level and IP level verification