ATCHYUT SREEKAR D

ASIC Integration

• Key contributor to the product development roadmap from controller kickoff to QS of the product
• Architected the ROM flows for UFS controllers and implemented new features to reduce controller boot time
• Led the bring-up efforts for Taped-out Silicons. Achieved Power-On flow enablement in less than 24 hours of Silicon Arrival in the Lab
• Took ownership of ROM and HAL for all MNAND next gen controllers – Drove the team to become a global Centre of Excellence
• Involved in System Architecture reviews, FW Architecture Design, ROM/HAL Development, System Engineering/Issue debug
• Ideated and built the ASIC Integration team of 20 members under MNAND division of Micron
• Mentored and enhanced the team's skillset in Controller ROM and HAL development, HW-FW debugging skillset with effective use of debug tools and debug FW

Crex SSD

• Bring up of ROM Code and Bootloader
• Redesign of Bootloader for memory availability
• Stabilization of Complete Boot sequence
• Implement Diagnostic Command Framework to establish communication between NAND Flash and diagnostic tool
• Development and stabilization of Low Level module essential in communication with the NAND

Establish NVMe-oF using Soft-RoCE on Linux

• Configure existing NIC to use Soft-RoCE protocol above ethernet protocol
• Did performance benchmarking of Soft-RoCE vs Ethernet using Intel MPI Benchmark
• Simulate SSDs on Linux using NVMe emulator
• Established bridge network interface between Guest FEMU OS and Linux OS for SSD network discovery
• Wrote an application to pass NVMe commands over Soft-RoCE and establish communication between the SSDs

Multi-Channel Video Encoder using H264 encoder

• Modify existing driver to add support for Multiple channels with different widths and heights
• Modify driver to pass a Full HD frame as multiple lower resolution frames to different channels of Encoder
• Added a Muxer code to convert encoded elementary streams to Transport streams and send them over UDP using FFMPEG libraries

CNN accelerator HW IP

• Modeled a SystemC based simulator using Winograd based convolution approach to replicate hardware functionality
• Extending the simulator to model other hardware like DataFlow Processor and Memory units

Implement TinyYOLO on SoCtronics DSP

• Establish communication between two DSP clusters through ARM
• Used one DSP cluster for Object detection and one for video encoding
• Implemented Softmax based classification and Object detection in kernel
• Overlay bounding box information on Video frames passed to encoder
• Stream encoded frames as packets through UDP

Develop SVAC2.0 Encoder on SoCtronics DSP

• Implemented Rate Control feature required for VDSP in the kernel using NEON
• Kernel porting from 3.4.55 to 3.12.71
• Establish communication between ARM host and DSP co-processor
• Modify existing driver to add functions required for SVAC 2.0
• Manage interrupts and synchronization between host and DSP co-processor
• Port code from simulator to device

Ineda Yantra Bringup

• Developed OS Independent HAL for UART and GPT timer which work on Linux and RTOS
• Developed test cases and validated memory and peripheral access for Cortex-M4 MPU and cache for Ineda Yantra board
• Found and reported secure access issues with Cortex-A5 processor
• Developed IoT application to receive sensor data and plot a graph in real-time using Python, NodeJS and MQTT client

Porting Tizen OS on Ineda’s Dhanush Microcontroller

• Involved in writing a DRM/KMS driver for Hardware Acceleration
• Worked on xorg-server and enabling hardware acceleration on the platform
• Worked extensively at user-level to build and run modules required for enabling xorg-server to work with Hardware acceleration
• Set-up custom cross-compiler toolchain for building OS
• Enabled SMACK for Linux Kernel
• Ported kernel from 3.10.x to 3.18.y
• Resolved hardware dependencies to enable modules for Hardware Acceleration