Atul Kabra

Analog Design Engineer(Staff Engineer)

Synopsys

03.2018 - Current

Optimized the Ethernet 56G-LR Receiver Analog Front End in TSMC 16nm while working alongwith System team to improve Receiver performance for improving the quality of the IP for customers.
Conducted circuit simulations for Ethernet 56G-LR Receiver top level design to verify the functionality of the different blocks in Receiver.
Conducted circuit simulation for Receiver Analog Front End & ADC in Ethernet 56G-LR after the design was ported from TSMC 16nm to 12nm.
Involved in Architecture level discussion and the design of Receiver Analog Front End( CTLE & VGA) for Ethernet 112G-LR Testchip in TSMC 7nm.Provided spice simulation data for Receiver Analog Front End to System team for the verification of RX performance and thereby also optimizing to design after feedback from System team.
Designed Ethernet 112G-LR Receiver Analog Front End(CTLE & VGA) in TSMC 6nm , 5nm and 4nm respectively.Conducted circuit simulation at Analog Front End top level to check and document all the necessary parameters for Analog Front End(i.e. Boost,Gain,Rms noise,THD etc).
Worked closely with System team for Ethernet 112G-LR IP and took necessary design for design changes in CTLE & VGA to improve the performance of Receiver hence improving the quality of the IP.
Involved in multiple customer engagement for design level discussion related to Receiver Analog Front End for both Ethernet 56G-LR IP (TSMC 16nm and 12nm) and Ethernet 112G-LR IP (TSMC 7nm and 6nm).
Involved in multiple customer and internal silicon debugs for 56G-LR and 112G-LR IP.
Debugged TX jitter performance degradation on silicon for 112G-LR IP in TSMC 5nm and provided the necessary solution to the Digital design team to fix the bug.
Improved the performance of Receiver loopback path (56G-LR and 112G-LR) for Transmitter to Receiver internal data loopback through different layout and design optimization techniques.
Conducted 112G-LR(multi-protocol) Receiver Analog Front End circuit simulations in TSMC 7nm and 6nm to verify the design for different Receiver input PAD bumps configuration for different customers.
Currently working on PCI Express Gen 7 IP for Transmitter to Receiver internal data loopback circuit.

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