Playing Cricket
Azarudeen A
System Validation Engineer
Bangalore
Summary
Tenured Hardware Engineer with 7+ years of pre and post Silicon validation experience. Strong Experience in Emulation and silicon bring-up, test-plan creation, and execution. In-depth knowledge of video HW and high-level SOC architecture. Capable professional with a keen eye for detail, exceptional multi-tasking capabilities, and advanced technical knowledge-seeking role.
Overview
7
7
years of professional experience
6
6
years of post-secondary education
4
4
Languages
Work History
System Validation Engineer
Intel Technologies India Pvt
Bangalore
04.2021 - Current
- Understanding Hardware Architecture Specifications and creating test validation plan for IP. Reviewing with all stack holders for Quality test validation plan
- Collaborating with 3rd Party IP/tools/ FW teams to complete the development and validation service requirements
- Taken ownership, Leading and delivered the Parti Service for Media concurrency development and validation with Media FW & Media parti framework from the Scratch
- Parti is a System Validation and Firmware Co-validation tool functioning both as a Firmware test and System Validation concurrency framework. Primarily used for high job count(at scale of 100000s and more) concurrency tests making use of ring buffers, work queue managers, and Process Address Space IDs
- Taken ownership crated all test plans for Telemetery, RAS & PRD’s coverages and mitigation
Member of technical staff
Mirafra software Technologies Pvt. Ltd
Bangalore
10.2020 - 04.2021
- Creating/Modifying/Improving test framework for System Level Testing
- Instrumental in bringing up the new Video analytics core for an
automotive chip along with validation of Functional Safety Features - Taking the complete ownership of IP validation starting from Emulation till it reach CS
- Improved the coverage at both IP and SOC level
Executing the validation plans, achieving the milestones on or before the time - Developed the automation scripts using python/Trace32 cmm for faster execution
- Measuring and debugging Power numbers(Voltage & Current) in Kratos Power measuring tool
- Capturing Bandwidth numbers by using DragonView tool
- In a VT project, found 1 Design Bug in Pre-si, which was an out-of-scope item in Emulation platform. Filed 1 Design CR/6 Doc CRs in same project. All Doc CRs led to change in Video sequence for HPG
- Proactively completed the 80% Video Validation in ES time frame, which is 1 month from SOD. Completed the SOD plan before 1 month of CS (remotely setup)
Senior Validation Engineer
Mirafra software Technologies Pvt. Ltd
Bangalore
10.2018 - 10.2020
- Understanding Hardware Design Document
- Understanding the specification document Hardware Program guide
- Understanding the Module design Delta overview
- Preparation Pre/Post Si validation test plan& feature coverage overview
- Taken ownership of completed module and validating all functional feature coverage
- Measuring and correlation of Power and Performance(PnP) of video Module
- Validating UBWC use-case between all other Multimedia Modules
- Validating system Concurrent use-case scenario across all other Multimedia Modules
- Delivering the system test /End User testcase across all SOC corners for video
- Proactively involving and debugging the Hw/Sw Issues
Software Engineer
Emware Technologies Pvt.Ltd
Bangalore
09.2015 - 10.2018
- Understanding the IP specification and how the specification is mapped on target SOC
- Identifying, Listing, Tracking and reviewing the features to be validated Align with Design/Soc DV/SW/FW teams to understand the design delta changes across the SOC’s
- Worked on Functional validation of Low and High Speed 32 bit peripherals like SATA, SPI, I2C, and UART serial communication protocols
- Preparation system level test plan and developed code for the compliance features IP
- Developed test cases for regression testing and stress testing
- Debugged with various other SOC sub system if required
- Prepared system level test plan
- Coordinated with the clients
Education
B.E - Electrical & Electronics Engineering
Institute of Road And TransportTechnology
08.2012 - 05.2015
Diploma - Electrical & Electronics Engineering
C.S.I Polytechnic College
06.2009 - 05.2012
S.S.L.C -
Bharathi Vidyalaya Hr. Sec School
06.2008 - 04.2009
Skills
C, Embedded C and AssemblyOperating system : Linux (Ubuntu), Windows
Pre/Post Silicon Validation
Multitasking & Mentoring
Developing Testplan
Analytical skills
Lab environment & Debug tools
Accomplishments
- Working on Pre and Post Si validation of Intel x86 SOC server accelerator IP– Content Processing module Media.
- Worked on Qualcomm Snapdragon Multimedia module (Video) on various SOC’s
- Worked on various Fabrications SOC’s such as 15nm to 4nm
- Worked on video Subsystem for the full life cycle on SD50X(1st 5G chip) SDM660,SDM630, SDM710, SDX50
- Worked on SATA, SPI, I2C, and UART serial communication protocols
- Strong in C Programming, Embedded C Programming and Debugging
- Experience with Functional Power and Performance Measurement (PnP) (Leakage, Standby, Dynamic)
- Work Experience on Pre -Post Silicon Validation of various subsystem IPs of SOCs
- Work Experience in developing of test cases/test plan for validation of different IP’s
- Good understanding of IPs specification and listed out all the features to be verified
- Work Experience in 32bit ARM Architecture and Tensilica Processors
- Extensively used Perforce, GIT tool for code and documentation check in and check outs
- Extensively used Kratos & DragonView tools for Functional Power and Performance Measurement (PnP)
- Hands on experience with validation of functional characterization such as Clock gating, DCD, DCG & Dynamic Clock-Voltage Scaling (DCVS)
- Actively interacting with team and designer to improve the quality of work
- Proactively involving and debugging the Hw/Sw Issues
- Proven ability to manage multiple projects while meeting challenges and Adaptability to work with different technologies on different platforms
Affiliations
- Honored by multiple Department and Hero/Shero Awards for CPM validation as team player
- Gladiator Award (2020) – For Excellence performance in the Pre and Post Si Validation as team player.
Interests
Gym Training
Volunteer work
Timeline
System Validation Engineer
Intel Technologies India Pvt
04.2021 - Current
Member of technical staff
Mirafra software Technologies Pvt. Ltd
10.2020 - 04.2021
Senior Validation Engineer
Mirafra software Technologies Pvt. Ltd
10.2018 - 10.2020
Software Engineer
Emware Technologies Pvt.Ltd
09.2015 - 10.2018
B.E - Electrical & Electronics Engineering
Institute of Road And TransportTechnology
08.2012 - 05.2015
Diploma - Electrical & Electronics Engineering
C.S.I Polytechnic College
06.2009 - 05.2012
S.S.L.C -
Bharathi Vidyalaya Hr. Sec School
06.2008 - 04.2009