Azaz Ahmad

I have worked 1 year 1 months as a google app store application reviewer.

Key Responsibilities:

• Application Evaluation: Conducted thorough reviews of applications submitted to the Google App Store, ensuring they met the platform's guidelines and standards.
• Quality Assurance: Assessed the functionality, usability, and overall quality of applications, identifying any bugs, glitches, or performance issues.
• Compliance Check: Verified that applications complied with Google’s policies, including content guidelines, privacy policies, and security standards.
• User Experience Analysis: Evaluated the user interface (UI) and user experience (UX) design to ensure a seamless and intuitive experience for end-users.
• Feedback Provision: Provided detailed feedback to developers, highlighting areas for improvement and suggesting best practices for app optimization.

• Hands-on training in ASIC physical design flow using industry-standard EDA tools.

• Gained expertise in floorplanning, placement, clock tree synthesis (CTS), routing, and signoff.

• Worked on real-time projects to understand design challenges and optimization techniques.

• Exposure to industry best practices for DRC, LVS.

Key Responsibilities:

• Block-Level Place-and-Route (PnR):Executed block-level physical design tasks including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and optimization for timing, power, and area (PPA).
• Managed congestion analysis and mitigation to ensure design routability and DRC-clean layouts.

Roles and Responsibilities:

• Block level PnR, ECO implementation & final verification.

• Handling all block level issues including PV to achieve Quality Tape out.

• Completed 2 Tape outs in currently working on two Project in PnR implementation.

Challenges:

Project-IV Handling Block level PnR implementation from Floorplan to Signoff, 4 nm technology, 1.2GHz frequency.

Project (Polaris B0)

Tool Innovus

• Presently working on setting up block level flow flush with the floorplan creation for the latest released input collaterals and making runs with different recipe settings for achieving optimized results.

• Analyzing flow setup and runs QoR results.

• Working with constraint updating, as lot of constraints and clock grouping definitions are missing in the SDC.

Project-III: Worked on flow setup for make Edition2.0 Block level PnR implementation flow from Floorplan to Signoff

Project (PnR EDISION2.0 FLOW)

Tool - Innovus

• Working closely with the new Edision2.0 flow. Flow was basically having some automated feature compared to the previous make flow.

• working on setting up block level flow flush. Updating for every stage from Floorplan to Signoff.

Project-II: Handled a block of 3 nm technology, 1.5 M instruction count, 3 GHz frequency. Worked on setting up the PnR to GDS flow.

Project (SMSM)

Tool - Innovus

• Working closely to PnR flow and also on CTS to fix latency issues. Placed Clock Root Buffers manually to fix latency issues.

• I have done custom placement for data pat-hand clock path for critical path as frequency is high.

• Manually routed a lot of nets in critical path in high layer to fix setup violations.

• Had to do lot of manual work with skewing techniques for setup and avoiding IR & DRC critical areas.

• Developed basic RM flow from floorplan to Sign-Off Gds.

Project-I: Handled a block of 5 nm technology, 1.2M instance count, and 3.2 GHz frequency.

Project (SAINTL)

Tool - Fusion Compiler

• Working closely with design team giving proper feedback Macro placement and other checks reports for better convergence.

• Analyzing different issues seen at each stage during PnR and working out solutions to create best recipe.

• Tried different techniques in ECO phase to reduce DRC’s and shorts in routing critical regions like downsizing/deletion of non-critical cells, spreading cells and manual-routing and manually moving-some cells in congestion critical area to non-critical area.