Summary
Overview
Work History
Education
Skills
Timeline
Generic

Bala Prasad

Hyderabad

Summary

Offering over 20+ years of experience with proficiency in technical disciplines & quality strategies to successfully integrate business needs for VLSI Physical Design. Executed various Techno Managerial roles in companies like INTEL, AMD ,Qual CoreLogic, TTM, TI, National Semiconductors

Overview

22
22
years of professional experience

Work History

Engineering Manager

Intel Corporation
Hyderabad
11.2016 - Current
  • Executed P&R implementation of multiple soc’s of sizes ranging from 16sqmm-200sqmm
  • Executed P&R implementation of sub systems like GPU, CPU (sifive), HBM3, DDR, PCIEGEN5, USB, validating IP PPA, process and in enhancement in Flow Methodologies.

Senior Design Engineer

SM Silicon
Hyderabad
11.2012 - 11.2016
  • Executed P&R implementation of multiple soc’s of sizes ranging from 16sqmm-200sqmm
  • Executed P&R implementation of sub systems like GPU, CPU (sifive), HBM3, DDR, PCIEGEN5, USB, validating IP PPA, process and in enhancement in Flow Methodologies.

Senior Physical Design Engineer

AMD Technologies
Hyderabad
03.2008 - 11.2012
  • Involved in tape outs of AMDs Graphic and APU soc chips
  • In the role of Block Lead & Block Owner for different blocks, responsible for P&R execution from net list to GDS including Physical Verification and managing a group of 5 to 10 engineers
  • Also responsible for Pre-Timing analysis on full chip timing for the clocks owned.

Physical Design Engineer

TTM India Pvt Ltd
Hyderabad
- 03.2008
  • Floor plan, Place and Route, physical verification of partitions
  • Led implementation of custom layout project with team size of five at National semiconductor
  • Addition responsibility of training and bringing up the new custom layout Team.

Asic Engineer

Qual core logic
Hyderabad
06.2005 - 02.2007
  • Involved in the execution of custom layout analog and RF blocks of the Wireless mixed signal chips for the client Texas Instruments
  • Key activities include Floorplanning, Routing, Extraction, DRC and LVS, ESD and Latch up checks, Antenna Verification, metal filling.

Asic Trainee Engineer

TTM India Pvt Ltd
Hyderabad
09.2004 - 06.2005
  • Undergone Training in the Physical design and involved in the block level P&R starting from netlist to GDS and design closure.

R&D Engineer

Samhita Systems
Hyderabad
09.2002 - 06.2005
  • Development of Hardware designs and testing the Boards (power electronics –ups, inverters, smps etc) and signoff the Boards with respect to specifications.

Education

Skills

  • Project Management :

Executed various senior roles like Sr Engineering Manager, SoC PD Lead, Sub-System Leads, Ramping-up size of 30 people and Mentoring teams in various MNC’s Also, executed E2E complete product in start-ups

  • Business Strategy Planning : Involved in Product Development Cycle in various technologies nodes includes IP Compatibilities, Cross Team and Multi site management, Resource planning,
  • Systems/Blocks :Place &Route execution from RTL to GDS including Physical Verification and timing sign off
  • SOC : SOC integration includes full chip floorplan, integrating IP’s, IO planning, Bus planning, bump planning (Die file/package) ,RDL Routing, DRC/LVS/IR/ESD , timing closure at SOC
  • Methodology :Active participation in customization of sub system and full chip flows and methodologies for quality and design cycle
  • Technologies :Intel 7nm, 10nm, 14nm & TSMC 5nm, 7nm ,16nm, 28nm
  • Tools : Cadence, Synopsys, Mentor graphics ,

Timeline

Engineering Manager

Intel Corporation
11.2016 - Current

Senior Design Engineer

SM Silicon
11.2012 - 11.2016

Senior Physical Design Engineer

AMD Technologies
03.2008 - 11.2012

Asic Engineer

Qual core logic
06.2005 - 02.2007

Asic Trainee Engineer

TTM India Pvt Ltd
09.2004 - 06.2005

R&D Engineer

Samhita Systems
09.2002 - 06.2005

Physical Design Engineer

TTM India Pvt Ltd
- 03.2008

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Bala Prasad