BALAJI JANAPALA

• Leading system-level memory validation across Mobile, Compute, XR, and Automotive SOCs; managing a team of four engineers.
• Drove the bring-up and validation of 25+ chipsets, ensuring readiness from silicon to customer release.
• Designed and executed end-to-end validation strategies, including concurrency, stress, and real-world workloads across multiple IPs.
• Generated complex, multi-master traffic patterns to validate system bandwidth, arbitration, and corner cases.
• Owned customer RMA issue debug, driving root cause analysis from logs to hardware using JTAG/T32.
• Enabled critical DDR features: frequency scaling, low-power modes, shmoo /eye margin validation.
• Built scalable validation frameworks and automation, significantly improving validation efficiency.
• Collaborated cross-functionally with HW, FW, SW, and architecture teams for issue closure.
• Facilitated onboarding for interns and new employees on SOC architecture and memory vector activities, promoting team competency.

AI-Driven Validation Contributions - Extensively used in-house AI tools for:

• Code walk throughs and architecture understanding.
• Rapid code modification and optimization.
• Framework development and enhancement.
• Debug acceleration and root cause isolation.
• Reduced manual debug effort significantly by automating analysis and issue triaging using AI-assisted workflows.
• Leveraged AI to accelerate workload generation and validation content creation, improving turnaround by approximately 5–6 times.

• Led system-level concurrency, PVT, DPMO and stress validation for Intel client chipsets.
• Designed cross-IP workloads to validate real-world system interactions and corner cases.
• Performed deep debugging across BIOS, OS, and hardware layers using trace and debug tools.
• Reduced validation cycle time from 3 weeks to 1 week through optimized execution strategies.
• Strong understanding of CPU architecture, power states, and interconnect behavior.
• Mentored new hires, and contributed to technical hiring and ramp-up.

• Driven end – end testing of Qualcomm chipsets from SOD to Customer sample.
• Core BSP SOC Infra Drivers validation that includes, ICB, Clocks, TSENS, GPIO/TLMM, DDR and I2C on Android & Windows chipsets.
• Experienced in both HLOS and Non HLOS driver’s validation.
• Expert knowledge in Board bring-up, Platform validation and Failure analysis/Debugging.
• Led stability validation and developed tools for comprehensive stability testing.
• Collaborated daily with dev and customer engineering teams to reproduce customer issues and provide initial debug information.
• Have considerable experience in training new hires on Automation, Mobile architecture, and Pre/Post silicon validation. Well versed with ticketing systems like JIRA and PRISM.

• Worked on eMMC/iNAND validation, including wear leveling and endurance testing
• Developed automated test cases and benchmark validation (IOMeter, ATTO)
• Gained strong foundation in NAND behavior and storage validation

• Validated core BSP drivers for IPs TSENS and ICB on mobile chipsets.
• Developed test automation scripts using PERL to streamline testing processes.
• Achieved successful project outcomes by maintaining accurate documentation and meeting strict deadlines.