BAMA ARULPRAKASAM
BTECH ELECTRONICS AND COMMUNICATION ENGINEERING
Thanjavur
Summary
- Cadence Virtuoso: Analog IC schematic, layout, and Spectre simulations
- Cadence Innovus: Floorplanning, placement, routing, and signoff checks
- Verilog: RTL coding and functional verification
- Post-Layout Simulation: Parasitic-aware validation for chip tapeout
Overview
1
1
Certification
Work History
PROJECTS
Designed a two-stage CMOS operational amplifier with reduced input offset voltage using circuit-level techniques
- Implemented and simulated in Cadence Virtuoso (180-nm GPDK)
- Achieved improved DC offset, gain, phase margin, and power efficiency
- Paper submitted to IIT Palakkad Conference
Winter Internship – IC Design & Fabrication, Chandigarh
Designed a fast-lock PLL achieving 1.4 µs lock time through optimized loop dynamics and block-level verification.
Gained practical exposure to foundry-level IC design flow and chip tapeout constraints.
Education
Bachelors of Technology - Electrical, Electronics And Communications Engineering
SASTRA Deemed University
Thanjavur, India 04.2001 -
Skills
Problem-solving
Certification
• VLSI Design and simulation training • Completed ‘Introduction and MATLAB & SIMULINK’ from SASTRA
Timeline
• VLSI Design and simulation training • Completed ‘Introduction and MATLAB & SIMULINK’ from SASTRA
07-2025
Bachelors of Technology - Electrical, Electronics And Communications Engineering
SASTRA Deemed University
04.2001 -