Summary
Overview
Work History
Education
Skills
PAPER PUBLICATIONS
Certification
Timeline
Generic

BEULAH GRACE NEELAM

GUNTUR

Summary

Highly productive VLSI Verification Engineer with expertise in SystemVerilog, UVM methodologies, and functional coverage techniques. Skilled in problem-solving, teamwork, and adaptability to drive successful project outcomes.

Overview

2
2
years of professional experience
1
1
Certification

Work History

Test Bench Implementation of Memory Using Verilog,

ETHERNET MAC
Bangalore
12.2022 - 04.2023
  • Designed and implemented a comprehensive test bench for memory modules using Verilog, focusing on validating functionality, timing, and performance parameters essential for Ethernet MAC applications.

Design and Modelling of Nano-wire Junction-less IS

Vignan Lara
Guntur
12.2020 - 08.2021
  • Developed a comprehensive model of a NW JL ISFET , focusing on its electrostatic characteristics and performance metrics to enhance sensitivity for biochemical applications.

Education

TRAINING - VLSI FRONT END TRAINING

VLSIGURU
Bangalore
04-2023

M.TECH - VLSI & Embedded Systems

V R Siddhartha Engineering College
VIJAYAWADA
09-2021

B. Tech - Electronics And Communications Engineering

Vignan’s Lara Institute of Tech & Science
Guntur
04-2019

Skills

  • Verilog
  • System Verilog
  • UVM
  • Python
  • Xilinx
  • Comsol
  • ModelIsm
  • Questa SIM

PAPER PUBLICATIONS

  • Title: Performance Analysis of Ion-Sensitive Field Effect Transistor with Various Oxide Materials for Biomedical Applications.
  • M. Durga Prakash, Nelam Beulah Grace, Shaik Ahmadsaidulu
  • DOI: https://doi.org/10.1007/s12633-021-01413-9
  • Published on 02, October, 2021

Certification

  • Internship at Entuple Technologies on Design and Verification Using Verilog.
  • Certified in Design and Verification on Verilog, SV and UVM.
  • Participation Certificate in Faculty Development Program on “VLSI Circuits and MEMS Device Modelling: Recent Trends and Advancements

Timeline

Test Bench Implementation of Memory Using Verilog,

ETHERNET MAC
12.2022 - 04.2023

Design and Modelling of Nano-wire Junction-less IS

Vignan Lara
12.2020 - 08.2021

TRAINING - VLSI FRONT END TRAINING

VLSIGURU

M.TECH - VLSI & Embedded Systems

V R Siddhartha Engineering College

B. Tech - Electronics And Communications Engineering

Vignan’s Lara Institute of Tech & Science
BEULAH GRACE NEELAM