BHANU PANDE

• Establishing Company-wide best practices in IP design with emphasis on consistency and reusability
• Collaborating with stakeholders: IP team, Product lines, etc.
• Leading development infrastructures/generators for next-gen. System Architectures and IP design. Targeting project run-time reduction by ~30%
• Automated TestBench/Test-Suite generation and Automated Performance Analysis of Systems and IPs
• Automated Interconnect Configurators providing architecture exploration infrastructure to architects

• Spearheaded initiative to develop Reference Architectures for Customers with Core IP Portfolio and 3rd party peripherals (e.g. Coherent/Non-coherent NOCs, IOMMUs, DFS, PCIE, etc.)
• Released more than 6 Reference Platforms in 2 years, with bare-metal and Linux/RTOS Boot supported platforms
• Showcased products: X390, X280, P650, E6-A, IOMMMU, etc.

• System level Performance analysis on Tegra Orin and Grace-Hopper.
• Running artificial and real customer use-cases as system level tests for measuring system QoS.
• Varying performance targets based on SCF/MCF and DDR frequency steps and data handoffs
• Modulating system QoS knobs evaluating efficiency of Memory Subsystem QoS with SPECint 2017

Virtual Prototyping with SystemC

• Lead TLM2.0 based SystemC model development of processor platform to enable early software-prototyping

Custom Coprocessor/Accelerator Enhancements

• Enhanced addressing using Segment Register
• Indirect Atomics supporting register-based masking
• Next-line Instruction-prefetcher
• Event-window with out-of-order event scheduling with dynamic+programmable priorities
• In-order Dual issue with dependency handler and precise exception handling
• Tail Recursion Optimization
• Developed Debug-architecture compatible with ARM CTI/M for system level halt/resume and pipeline observability
• Suggested Instruction Compression and Decompression scheme for improving code density

Fractional Sample Rate Converter

• Patented design innovations in a Fractional Sample-rate converter design
• Primary focus on reducing the input-stage multiplexing congestion
• Software-assisted preload of coefficients utilizing repeatable pattern in the indices

Signal Processing Datapath

• Designed JESD data compression engine and fractional clock divider
• Architected/Designed a Multi-band Digital Automatic-Gain Controller algorithm for wide-band high-speed receivers

Processor Platform

• Spec-to-implementation ownership of 1st processor subsystem for High-speed Converters
• Design/Architecture ownership of the Clock, Reset, Power Management unit, SPI-AHB Bridge, AHB-APB Bridge, etc.
• Owned the entire implementation-flow (Synthesis-to-Route)