Bhanu Thumpati

System Engineering

• Developed CP-compatible, firmware-based test suite to catch memory marginality under extreme PVT stress; enabled early detection of retention issues undetectable by MBIST, reducing fabrication yield loss through in-fab deployment.
  .PVT Corners .CP-Compatible .Memory Marginality .Yield Optimization
• Aligned the Backend codebase of the Platform Firmware from B58R to B68S, successfully establishing handshake between Frontend,Backend,NAND.
• Designed low-power test sequence with inter-core coordination and gated power domain transitions to uncover cell instability during retention cycles; exposed failures triggered only during power gating and corner drift.
  .Low-Power States .Power Gating .Power Domains .Retention Failures
• Updated platform firmware and ROM to support a new compiler and linker configuration,followed by comprehensive regression testing to ensure stability.
• Implemented dynamic LFSR-based random traffic and tag-aware back checks to stress fabric interconnects under concurrent loads; revealed timing hazards and transient errors via inter-core communication under real-world access patterns.
  .LFSR Stress .Concurrency .Interconnect Faults .Inter-Core Communication
• Proposed a revised low-power sequence to prevent ONFI timeouts. Conducted phased firmware experiments with MDLL clock gating and delay sequencing; debugged via signal analysis on LA to identify FSM stalling due to disabled final tracking, leading to sequence revision.
• Proposed a Fix to mitigate Transient Bit Flips on Tx-L2 cache Buffer of Data Link Layer in Device UNIPRO, updated Capability of Unipro FSM for successful exchange during PMC changes in High Gears.
  

FAFW
Developed failure analysis firmware for corner case detection in automotive and mobile controllers. Created a multi-stage diagnostic firmware to identify hard-to-reproduce failures in field-deployed controllers. Stripped irrelevant code to optimize size for HS core and coupled memory. Disabled FTL features (e.g., wear leveling, garbage collection) to run bare-metal stress tests at the HAL level.

ROM

• Developed Rom Patching solution to faulty UFS_RESET, VDET ISR's by fetching Instructions from ROMCONFIG page to ARC ICCM in BFN flow to mitigate bootstuck and prevented controller Re-spin.

• Initialized RAIN Parity generator in ROM,Configured fabric protocol (IBC) for controller cores (Hs0) and DMA, facilitating efficient communication. Brought up BOOTSTRAP to carry out functional testing in the ROM environment,utilized Synopsis Metaware for debugging purposes. Successfully passed test vectors from the host through UFS by configuring routing rules and establishing new UFS, UART vendor commands on the device (controller)
• Reviewed Existing UART serial communication protocol and optimised IP to support full duplex communication for Enhanced performance ,Utilized FIFO buffers to improve synchronization and ensure robust data transfer . Made code changes to improve the overall clarity and readability of the implementation. Conducted thorough testing and verification to ensure the functionality and reliability of the modified UART IP.