ASIC Digital Design Engineer
Synopsys
Bengaluru
03.2023 - Current
- Executed USB 3x, USB 2.0 IP design and verification using Verilog and System Verilog, enhancing protocol knowledge, along with interface protocols such as UTMI, PIPE protocols.
- Contributed to microarchitecture-level design and implementation with focus on Power, Performance and Area Optimization.
- Experience with bus protocols like AHB/AXI.
- Developed power-aware RTL designs with Unified Power Format to enhance system efficiency.
- Applied clock-gating techniques to analyze metrics like Clock Gating Efficiency and Data-Aware Clock Gating Efficiency.
- Performed static checks, including CDC, Lint, and RDC, for RTL coding and simulation accuracy.
- Utilized EDA tools such as Spyglass, VCSpyglass, Design Compiler, VC Formal(AEP, FPV, SEQ), and VCS to support project development.
- Handled customer cases for technical clarifications.
- Leveraged AI models to streamline processes, reducing manual effort and increasing overall operational efficiency.
- Automated repetitive tasks through Python scripting, improving workflow and allowing the team to focus on higher-priority tasks.
- Mentored colleagues and organized team-building activities to foster collaboration.
- Alongside organized site-level CSR events and activities.