Open To Work
Bharath G S
BENGALURU
Summary
Experienced ASIC Digital Design Engineer skilled in RTL design, power optimization and hardware validation, with a strong background in automation and AI integration. Proficient in EDA tools, contributing to innovative IP design and verification solutions. Committed to enhancing team efficiency and continuous improvement.
Overview
6
6
years of professional experience
1
1
Certification
Work History
ASIC Digital Design Engineer
Synopsys
Bengaluru
03.2023 - Current
- Executed USB 3x, USB 2.0 IP design and verification using Verilog and System Verilog, enhancing protocol knowledge, along with interface protocols such as UTMI, PIPE protocols.
- Contributed to microarchitecture-level design and implementation with focus on Power, Performance and Area Optimization.
- Experience with bus protocols like AHB/AXI.
- Developed power-aware RTL designs with Unified Power Format to enhance system efficiency.
- Applied clock-gating techniques to analyze metrics like Clock Gating Efficiency and Data-Aware Clock Gating Efficiency.
- Performed static checks, including CDC, Lint, and RDC, for RTL coding and simulation accuracy.
- Utilized EDA tools such as Spyglass, VCSpyglass, Design Compiler, VC Formal(AEP, FPV, SEQ), and VCS to support project development.
- Handled customer cases for technical clarifications.
- Leveraged AI models to streamline processes, reducing manual effort and increasing overall operational efficiency.
- Automated repetitive tasks through Python scripting, improving workflow and allowing the team to focus on higher-priority tasks.
- Mentored colleagues and organized team-building activities to foster collaboration.
- Alongside organized site-level CSR events and activities.
Teaching Assistant
VLSI System Design
Bengaluru
11.2021 - 03.2023
- Teaching students about basics of VLSI flow, and ,mixed signal design.
- Facilitated student understanding through one-on-one tutoring sessions.
- Evaluated assignments and delivered constructive feedback, fostering student growth and comprehension.
- Tutored students on EDA tools to enhance their comprehension.
Analog Layout Engineer
ABCRL
09.2022 - 10.2022
- Employed matching techniques, including interdigitization and common centroid, to enhance layout performance.
- Utilized CustomCompiler for layout design of standard cells, ensuring design accuracy and efficiency.
- Created technical documentation for engineering processes, facilitating team collaboration and knowledge sharing.
Research Intern
e-Yantra, IIT-BOMBAY
06.2020 - 08.2020
- Developed hardware/software co-design concepts in VLSI on Zedboard using ForSyDe and CoFeldspar.
- Collaborated with team members to design and implement experimental methodologies.
- Conducted literature reviews to support ongoing research project at IIT-BOMBAY.
Education
M.Tech - Integrated Circuit Systems
Indian Institute of Madras
Chennai06-2028
B.E. - Electronics and Communication
B.M.S College of Engineering
Bengaluru06-2023
PUC/12th -
MIRANDA PU COLLEGE
Bengaluru04-2019
10th -
SRI CHAITANYA TECHNO SCHOOL
Bengaluru04-2017
Skills
- RTL Design and Verification: I have worked on multiple blocks in a complex USB3x, USB 20 IPs
- Power-aware design and Power reduction strategies: I have worked on power optimization techniques like clock/data gating, optimized FSM encoding, and reduced switching activity across data paths along with UPF aware designs
- EDA tools proficiency and Design tool expertise: I have used various tools, such as Fusion Compiler, VC Spyglass, and VC Static
- Digital signal processing : I have implemented signal processing algorithms into optimized designs with focus on performance, area, and power
- Automation scripting: I have written multiple scripts for efficient workflow and simple tasks
- Technical documentation: I have maintained multiple technical documents for the blocks designed
- Problem-solving mindset: I come with a problem-solving mindset for any given problem at hand
Affiliations
- Scuba Diver: Certified Advanced Open Water Diver
- Pastry Chef : I have a sweet tooth and enjoy baking; I have attended professional baking sessions as well.
- Guitarist: 1st-grade instrumental guitar, Trinity College, London.
- Amateur radio enthusiast: Call sign (VU3UCA).
- Martial Artist: I hold a black belt in karate with more than 10 years of practice.
Accomplishments
Peter, D., Bharath, G.S. (2025). Large Language Models for Energy Forecasting and Prediction in Renewable Energy Systems. In: Rane, N.L., Mallick, S.K., Rane, J., Pande, C.B. (eds) Large Language Models for Sustainable Urban Development. The Springer Series in Applied Machine Learning Springer, Cham. https://doi.org/10.1007/978-3-031-86039-3_3
A. G. Nayak, Bharath G S, I. Bhan, G. Mishra and V. Kumar, "A low voltage and low power analog multiplier," 2023 IEEE Fifth International Conference on Advances in Electronics, Computers, and Communications (ICAECC), Bengaluru, India, 2023, pp. 1-4, doi: 10.1109/ICAECC59324.2023.10560170 keywords: {semiconductor device modeling, low voltage, electric potential, power demand, scalability, layout, voltage, analog multipliers, flipped voltage follower, Gilbert multiplier, low voltage, low power}
Shashank T. K., Bharath G. S., Hitesh N., Meghana Bukkapatnam, and Shria Dhananjay Jadhav, 2022, “NB-IoT Based Road Accident Alert System,” International Journal of Engineering Research & Technology (IJERT) Volume 11, Issue 03 (March 2022)
Certification
- RISC-V RTL Design & Verification, 12 weeks , 2026
- Low power design, VSD IAT, 5 weeks , 2025
- Internet of Things using Pi and Arduino, Coursera, 16 weeks, 2022
Languages
- Kannada
- English
- Japanese
- German
Volunteering
- Rotaract Club of Indiranagar, Bangalore, Board of Directors (Professional Development), 2025-26
- U & I NGO, teaching the underprivileged, 2024-25,
- Make A Difference NGO, teaching the underprivileged, 2020-2024
Timeline
ASIC Digital Design Engineer
Synopsys
03.2023 - Current
Analog Layout Engineer
ABCRL
09.2022 - 10.2022
Teaching Assistant
VLSI System Design
11.2021 - 03.2023
Research Intern
e-Yantra, IIT-BOMBAY
06.2020 - 08.2020
M.Tech - Integrated Circuit Systems
Indian Institute of Madras
B.E. - Electronics and Communication
B.M.S College of Engineering
PUC/12th -
MIRANDA PU COLLEGE
10th -
SRI CHAITANYA TECHNO SCHOOL