Summary
Overview
Work History
Education
Skills
Certification
Debug Tools
Hobbies
Timeline
Generic

BHARATH SRIVATSA

Silicon Validation Engineer
Bengaluru,KA

Summary

  • Committed and Accountable Silicon Validation Engineer with over 15 years of extensive experience in the distinguished semiconductor organizations like Qualcomm and Intel.
  • Skilled in pre and post silicon validation of complex cutting-edge IP cores on Mobile, x86, IoT and Automotive SoCs
  • Expertise encompasses USB4v1 (40G) and USBv2 (80G) IP cores, retimer solutions and Camera ISP cores.
  • Proven track-record of implementing robust validation processes, development of comprehensive test plans and driving critical debug initiatives, resulting in the successful delivery of high-quality hardware across multiple projects
  • Ability to collaborate easily and efficiently with cross-functional teams fostering a culture of achieving technical excellence through collective purpose.
  • I try to keep things simple, communicate effectively, learn new skills, lead by example and stay grounded.

Overview

15
15
years of professional experience
4
4
years of post-secondary education
1
1
Certification

Work History

SoC Functional Validation Engineer

Intel
03.2019 - Current

Technology:

  • Thunderbolt/USB4 is a super speed IO hardware supporting a data rate of 40Gbps. It can tunnel USB3, PCIe and DP protocols and is the baseline for next-gen USB4v2 (80Gbps).
  • USB4 40G and 80G Retimer SoCs

Projects:

  • Alder lake, Raptor lake, Meteor lake, Lunar lake, Arrow lake, Panther lake and Nova lake(80G)

Responsibilities:

  • Senior member of technical staff and IP SV lead for USB4 core & Retimer across Intel Client SoCs
  • My role is to implement validation processes, define test methodologies, develop validation plans - test content, drive critical debugs and technical mentoring of peers. I believe this has helped foster a highly skilled and efficient USB4 IP SV team.
  • My scope of work also extends to tasks like HW bring-up during PON, alignment of technical deliverables with program management, representing my team in key decision-making forums and serving as the "sys-debug" PoC to cross-functional teams.
  • Successfully delivered production quality Thunderbolt/USB4 IP hardware to be integrated onto Intel SoCs (from Alder lake to Nova Lake) which included the world's first USB4v1(40G) and USB4v2(80G) host cores.
  • Successfully delivered 2 retimer SoCs (40G) and (80G) to be paired with USB4 cores on Intel SoCs
  • Debug lead driving root-cause analysis of issues during validation cycle, enabling timely resolution of HW or FW bugs through fixes/enhancements. This helps unlock critical project milestones and at times also leads to ECOs on the subsequent silicon step.
  • Collaborate with design, architecture, firmware, and software teams to ensure comprehensive coverage and resolution of validation issues.
  • Ensure the IP undergoes thorough product certification and compliance testing as per USB-IF guidelines.
  • Work with lab equipment such as oscilloscopes, logic analyzers, protocol analyzers, debuggers etc

Senior Lead Validation Engineer

Qualcomm
07.2011 - 03.2019

Technology:

  • Multimedia sub-system (Camera ISP/Video Core), CPU (ARM v7) sub-system, IoT modules

Projects:

  • Multiple Mobile SoCs spanning across Snapdragon 200, 400 and 600 series
  • CSR Smart Audio 400 (IoT SoC)
  • Snapdragon 820A (Automotive SoC)

Responsibilities:

  • My role as an individual contributor mainly involved performing bare-metal silicon validation of different IPs like camera (ISP core), video codec and CPU cores.
  • Development of a wide variety of test content to achieve complete validation coverage -> bare metal drivers, sanity tests, functional & system-level use-cases, stress and stability, concurrency scenarios, power and performance measurement/analysis.
  • Perform pre-silicon validation of IP cores on FPGA emulation platforms.
  • Responsible for all post-silicon activities associated with the IP starting from silicon bring-up to project EoL.
  • Perform characterization of IP-cores based on process, temperature, frequency and voltage scaling.
  • Support software and customer teams to debug software issues and OEM must-fix issues.
  • Deliver ATE vectors to enable easy screening of bugs on high volume parts.

DFT Engineer

Wipro VLSI
06.2010 - 07.2011
  • Integrating testability features into SoC through scan insertion, ATPG pattern generation and validation using Cadence or Synopsys DFT tools.

Education

Bachelor of Engineering - Electronics and Communication

PES University
08.2006 - 06.2010

Skills

  • Technical Project Leadership

  • Post-Silicon Validation

  • Test Plan and Content Development

  • Debug Methodologies

  • Hardware Architecture

  • Communication Skills

  • Lab Equipment

  • Pre-Silicon Validation

  • Programming and Automation

Certification

Advanced VLSI, Illinois Institute of Technology, IL, USA

Debug Tools

  • Lauterbach Trace32
  • Intel Python-SV Debugger
  • USB4 Diagnostic Tools
  • Ellisis Type-C PD Tracker
  • Logic Saleae Analyzer
  • Intel Trace Hub for sideband and VISA
  • Oscilloscope
  • Logic Analyzer
  • Lecroy M4x USB4 Protocol Analyzer
  • Power Analyzers like NI-KRATOS


*******************************************

  • Azzure VSTS frame work for automation
  • GIT & Perforce for version control
  • MS Office Tools

Hobbies

Audible books, Sports, Indian Mythology, Stories & Movies

Timeline

SoC Functional Validation Engineer

Intel
03.2019 - Current

Advanced VLSI, Illinois Institute of Technology, IL, USA

07-2013

Senior Lead Validation Engineer

Qualcomm
07.2011 - 03.2019

DFT Engineer

Wipro VLSI
06.2010 - 07.2011

Bachelor of Engineering - Electronics and Communication

PES University
08.2006 - 06.2010
BHARATH SRIVATSASilicon Validation Engineer