Bhavit Kaushik

Secure Device Manager

• Developing multiple IPs of SDM, including Clock and reset manager, boot flow controller, in addition to design control and status memory-mapped register, using Magillem IPxact.

Agilex 5: Sub-System Timing Owner

• Delivered the first structured eASIC Agilex 5 series, collaborating with the designer to understand timing specifications, clocking architecture, DFX architecture, and interface ACIO timing requirements.
• Contributed to shortened B0 stepping TAT by successfully identifying and fixing bugs through timing ECO during silicon debugging activities.
• Led timing convergence for critical partitions involving application processor subsystem and peripheral subsystem with a mix of coherent and non-coherent NOC, encompassing low to medium speed peripherals such as ethernet, USB, NAND, SPI, SDMMC, I2C/I3C, and UART. Operated on 10nm technology at clock speeds ranging from 0.2 GHz to 0.8 GHz.
• Converged timing for high-speed designs involving quad-core A76/A55 Processor tile and peripheral subsystems such as Ethernet/USB2/SPI/SDMMC.
• Assisted in crucial GPIO placement to ensure efficient peripheral SS closure.
• Demonstrated strong skills in exploring complex clocking architectures by successfully using reverse engineering to optimize constraint cleanup.
• Created custom SQL script for ACIO timing closure. Developed timing constraints for sub-system and provided feedback to designers, validated using Fishtail.
• Maximized performance of Quartus simulation tool by developing specialized timing models (.libs) for various operational modes.

Sub-System Timing Lead

• Led a team of 3 engineers, successfully closed timing at 0.5-1.8GHz with a level of logic of ~70 in SDM/MPFE block consisting of 3 partitions.
• Worked closely with PD team to help in faster IO closure by bounding and proper port placement.
• Conducted weekly convergence meetings with block owners to address and resolve common issues.
• Supported timing closure for various projects during ECO phase on temporary assignment.

Video Sub-System Timing Owner

• As SS STA lead, implemented automated ECO generation flow to improve fix-rate and aid timing closure of complex designs in time-stipulated projects.
• Successfully resolved hot spot and crosstalk challenges arising due to tighter PPA targets and ~1G frequency.
• Worked in tandem with EDA vendors, including Tweaker/PT-ECO for what-if Analysis.

SoC level timing convergence team

• Implemented script-based automation to manage full chip timing runs using Perl and Tcl.
• Managed top-level RC extraction & SoC timing runs for 450 corners while ensuring precise timing correlations to all designated partition owners.
• Delivered 4 successful SoC project tape-outs.

Timing Corner reduction and Budgeting

• Implemented dominant corner analysis to optimize resource allocation. Provided multiple budgeting flow enhancements to streamline processes. Delivered PD ready IO budgets for improved interface optimization.

• Oversaw both FP aware (FT and Combo) and non-FP aware budgeting.
• Resolved linking issues in MSM/MDM full chips for over 50 IPs and more than 500 corners while fixing scaling issues with missing .libs.

• Designed and implemented FPGA-based systems for real-time image processing applications in medical, security, weather forecasting, and image/video compression.