Brijesh Kumar
Verification IP R&D Engineer
Noida
Summary
Dynamic and result oriented Verification IP Engineer at Cadence Design Systems with expertise in Ethernet and UART protocols. Proven track record in developing and verifying complex features using C, SV and UVM. Strong problem-solving skills. Successfully enhanced customer support through effective bug resolution and feature implementation.
Eager to explore IP/SOC/CPU/GPU/ASIC verification domains.
Overview
4
4
years of professional experience
3
3
Certificates
Work History
Software Engineer II
Cadence Design Systems
12.2022 - Current
Key Responsibilities:
- Currently working as Verification engineer and Developer on serial protocols, Ethernet IEEE std 802.3 and UART.
- Ownership and development of UEC LLR feature in C and verification in UVM.
- Developed constrained random verification environment for UEC LLR.
- Development and verification of Inner FEC layer of 200G per lane speed mode.
- Provided active support to customers with VIP configuration, Bug fixes, Error scenarios and identifying DUT bugs on Pause, PFC, UEC LLR.
- Development and verification of IPV6 tunnel feature.
- Provided active support to customers with configuration and bug fixes on UART VIP and Extended features like IrDA, SmartCard, LIN Break, LPUART, ModBus.
- Development and verification of UART auto Baud rate detection and Noise insertion features.
Verification Engineer
Scaledge Technology
08.2021 - 12.2022
Key responsibilities:
- Worked as verification engineer on different projects.
- Worked on Ethernet MAC (10M/100M) functional verification, AXI VIP development in System Verilog, AMBA protocol (APB/AHB) UVC development using UVM.
- Develop Test Bench Architecture and implement.
- List down Ethernet MAC design features and develop test plan, verification plan for functional verification.
- Developed Test Bench components.
- Developed test cases and debug.
- Developed Functional Tests and debug.
Education
M. Tech. - Communication And Networks
National Institute of Technology
Raurkela, India 04.2001 -
B. Tech. - Electronic And Communication
Shri Mata Vaishno Devi University
Jammu, India 04.2001 -
Skills
Protocol Knowledge: Ethernet, UART, AMBA (APB, AHB, AXI)
HDL & HVL: Verilog, System Verilog
Methodology: UVM
Scripting: Python
Programming Languages: C/C
Tools: Cadence Xcelium, IMC, Questasim
Operating system: Windows, Linux
Certification
VLSI Internship at IITM Gwalior, M.P.
Timeline
Software Engineer II
Cadence Design Systems
12.2022 - Current
Verification Engineer
Scaledge Technology
08.2021 - 12.2022
Python Programming for Everybody, University of Michigan.
07-2021
Networking CCNA Workshop
10-2019
VLSI Internship at IITM Gwalior, M.P.
06-2013
M. Tech. - Communication And Networks
National Institute of Technology
04.2001 -
B. Tech. - Electronic And Communication
Shri Mata Vaishno Devi University
04.2001 -