Brijesh Kumar

Key Responsibilities:

• Currently working as Verification engineer and Developer on serial protocols, Ethernet IEEE std 802.3 and UART.
• Ownership and development of UEC LLR feature in C and verification in UVM.
• Developed constrained random verification environment for UEC LLR.
• Development and verification of Inner FEC layer of 200G per lane speed mode.
• Provided active support to customers with VIP configuration, Bug fixes, Error scenarios and identifying DUT bugs on Pause, PFC, UEC LLR.
• Development and verification of IPV6 tunnel feature.
• Provided active support to customers with configuration and bug fixes on UART VIP and Extended features like IrDA, SmartCard, LIN Break, LPUART, ModBus.
• Development and verification of UART auto Baud rate detection and Noise insertion features.

Key responsibilities:

• Worked as verification engineer on different projects.
• Worked on Ethernet MAC (10M/100M) functional verification, AXI VIP development in System Verilog, AMBA protocol (APB/AHB) UVC development using UVM.
• Develop Test Bench Architecture and implement.
• List down Ethernet MAC design features and develop test plan, verification plan for functional verification.
• Developed Test Bench components.
• Developed test cases and debug.
• Developed Functional Tests and debug.