Brijeshkumar Arvindbhai Savaj

Since joining as senior engineer at Qualcomm, I was responsible for multiple SOC layout signoffs at both block & SOC levels for around 8 yrs & 5 months.

Role included performing checks like DRC , LVS , ERC ,PERC , Antenna, DFM (PM, VRC Checks), and ESD to identify and flag any violations of design rules to concerned party & resolve them.

Working with CAD team at the start of new tech node for flow flush & finding new requirements for old tech nodes along with reporting & resolving DRC issues at any stage of PNR cycle.

Working with PNR team at each stage of the cycle like floorplan, Placement & tapeout, Analyzing critical issues which may impact floorplanning & drc closure at tapeout time frame was key part of the role.

Interactions with different stakeholder includes pdk team, IP team, std-cell/memory team, RDL team, CAD team, SOC floorplan team & PNR team.

Since Jan2024 I have been shifted to PNR task & since than contributed on 2 tapeouts & currently working on 3 project.

First design was a core which was close to 2M instance count, tsmc N4 tech node & PNR tool was FC. Challenges of block includes multivoltage domains, high number of macros including hard IPs like PLL, TS & Comparators. Design needs to meet 4 sigma hold & 5 sigma setup. Reducing congestion, always on buffering, secpg & pre-routes, ISO/LS placements & IO timing for SPMI logic were added issues.

Second design was tile which was wrapper with 1 identical DL2 instantiated 2 times. Design was ~3mil flat & lowsvs critical due to no freq scaling across modes. Design challenges included tsmc N3 tech node, first time 4 flatten hierarchy in to DL1 including 1 mx hierarchy, pipelines for 2 hierarchy, high number of ISO/LS imposed congestion challenges, 533MHz freq in low voltage corner posed CTS challenges, feedthrough addition for soc nets & lastly tight timelines.

Both the PNR task involved handling non-STA signoff flows like Formal verification, low power rules, PDN & PV closure. Interaction with stakeholders including synth team, soc floorplan team, cad team & signoff team.

• As Physical Verification Engineer at Qualcomm India Pvt Ltd. (through Mirafra software technologies) Started working on block level layout signoffs.
• These projects involved Physical Verification and providing QOR feedbacks at every stage of P&R implementation at different technology nodes (28nm,14 nm), which includes analysis and implementation of DRC, ERC, Softcheck, LVS and Antenna fixes.

• Contributed towards the Physical verification of next generation Xeon server’s designs. Responsible for cleaning up FUBs/Partitions that contain DRCs, LVS errors, Antenna issues. Additionally, implementing Engineering Change Orders (ECOs) from Design Engineers and making sure that the mask/layout is clean from any DFM errors.