Summary
Overview
Work History
Education
Skills
Accomplishments
Timeline
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Abhinav Krishna Ravuri

Abhinav Krishna Ravuri

Analog Design Engineer
Bangalore

Summary

Dynamic Analog Designer, hardworking and consistent in work, habituated to learn and grasp new things in considerable pace.

Overview

6
6
years of professional experience
6
6
years of post-secondary education

Work History

Analog Design Engineer

PI Semi (India) pvt ltd
Bangalore
07.2022 - Current

Responsible for design of low noise (2uVrms)(0.1Hz to 10Hz), low temperature drift (5ppm/C)(-40C to 125C) voltage reference of 2.5V.(Curvature corrected) (From scratch)

Responsible for design of bias currents generation both trimmed and untrimmed.(From scratch)

Responsible for design of a crude voltage reference, bias current generation circuit and several stand alone PTAT and CTAT current generation circuits.(From scratch)

Responsible for design of several opamps and a buffer.(From scratch)

Responsible for running simulations on a Rail to Rail input, Rail to Rail output amplifier.(Stability issues were debugged and sorted)(First task)

Junior Research Fellow

Defense Research and Development Organization
Hyderabad
10.2019 - 03.2020
  • Altimeter testing
  • Noise Figure and SNR calculations

Education

Master of Science - Integrated Circuits And Systems

Indian Institute of Technology
Madras
08.2020 - 06.2022

Bachelor of Technology - Electronics and Communication Engineering

Amrita School of Engineering
Bangalore
07.2015 - 08.2019

Skills

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Accomplishments

  • For EE
  • (CGPA = 8.6)
  • Bootcamp on designing a CTDSM of arbitrary specification
  • From
  • MATLAB simulations to ideal block level design in Cadence Virtuoso and LT Spice
  • Here I designed single bit, multibit and MASH CTDSM of given specification at block level
  • Understanding effect of clock jitter, loop filter non-linearity, DAC mismatch on the modulator performance and overcoming them by using techniques like FIR DAC,
  • Dynamic Element Matching(DEM) were key learnings from the boot- camp
  • For reducing area and power consumption, we reduced active summer to passive summer and used a single resonator (SAB, 1OTA) instead of two integrators(2 OTAs)
  • Designed Current Mode Bandgap Reference of 100nA using UMC 180nm technology in Cadence Virtuoso
  • Designed schematic, layout(DRC and LVS cleared) and parasitic extraction was done and the design was tested across all corners.

Timeline

Analog Design Engineer

PI Semi (India) pvt ltd
07.2022 - Current

Master of Science - Integrated Circuits And Systems

Indian Institute of Technology
08.2020 - 06.2022

Junior Research Fellow

Defense Research and Development Organization
10.2019 - 03.2020

Bachelor of Technology - Electronics and Communication Engineering

Amrita School of Engineering
07.2015 - 08.2019
Abhinav Krishna RavuriAnalog Design Engineer